Michael Wielgos

According to our database1, Michael Wielgos authored at least 5 papers between 2011 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS.
IEEE Solid State Circuits Lett., 2025

2024
A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

A 0.9pj/b 9.8-113Gb/s XSR SerDes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2022
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2011
A 16-Gb/s backplane transceiver with 12-tap current integrating DFE and dynamic adaptation of voltage offset and timing drifts in 45-nm SOI CMOS technology.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011


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