Gautam R. Gangasani
Orcid: 0000-0001-9834-5733
According to our database1,
Gautam R. Gangasani
authored at least 8 papers
between 2006 and 2022.
Collaborative distances:
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Bibliography
2022
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
2019
A 0.5 V, 9-GHz Sub-Integer Frequency Synthesizer Using Multi-Phase Injection-Locked Prescaler for Phase-Switching-Based Programmable Division With Automatic Injection-Lock Calibration in 45-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
2018
A 19Gb/s RX for VSR-C2C Links with Clock-Less DFE and High-BW CDR Based on Master-Slave ILOs in 14nm CMOS.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
2014
A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2014
2012
A 16-Gb/s Backplane Transceiver With 12-Tap Current Integrating DFE and Dynamic Adaptation of Voltage Offset and Timing Drifts in 45-nm SOI CMOS Technology.
IEEE J. Solid State Circuits, 2012
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
2006
A Time-Domain Model for Predicting the Injection Locking Bandwidth of Nonharmonic Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006