Alexandre E. Eichenberger

Affiliations:
  • IBM Research


According to our database1, Alexandre E. Eichenberger authored at least 51 papers between 1994 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

Online presence:

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Bibliography

2024
Serving Deep Learning Models from Relational Databases.
Proceedings of the Proceedings 27th International Conference on Extending Database Technology, 2024

2023
Serving Deep Learning Model in Relational Databases.
CoRR, 2023

2021
Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption.
IEEE Trans. Computers, 2021

2020
Hybrid CPU/GPU tasks optimized for concurrency in OpenMP.
IBM J. Res. Dev., 2020

An open-source solution to performance portability for Summit and Sierra supercomputers.
IBM J. Res. Dev., 2020

Compiling ONNX Neural Network Models Using MLIR.
CoRR, 2020

Language to Network: Conditional Parameter Adaptation with Natural Language Descriptions.
Proceedings of the 58th Annual Meeting of the Association for Computational Linguistics, 2020

2019
POSTER: CogR: Exploiting Program Structures for Machine-Learning Based Runtime Solutions.
Proceedings of the 28th International Conference on Parallel Architectures and Compilation Techniques, 2019

2017
Implementing implicit OpenMP data sharing on GPUs.
Proceedings of the Fourth Workshop on the LLVM Compiler Infrastructure in HPC, 2017

libPRISM: an intelligent adaptation of prefetch and SMT levels.
Proceedings of the International Conference on Supercomputing, 2017

Efficient Fork-Join on GPUs Through Warp Specialization.
Proceedings of the 24th IEEE International Conference on High Performance Computing, 2017

2016
Performance Analysis and Optimization of Clang's OpenMP 4.5 GPU Support.
Proceedings of the 7th International Workshop on Performance Modeling, 2016

Offloading Support for OpenMP in Clang and LLVM.
Proceedings of the Third Workshop on the LLVM Compiler Infrastructure in HPC, 2016


A Proposal to OpenMP for Addressing the CPU Oversubscription Challenge.
Proceedings of the OpenMP: Memory, Devices, and Tasks, 2016

2015
Integrating GPU support for OpenMP offloading directives into Clang.
Proceedings of the Second Workshop on the LLVM Compiler Infrastructure in HPC, 2015

Performance analysis of OpenMP on a GPU using a CORAL proxy application.
Proceedings of the 6th International Workshop on Performance Modeling, 2015

Exploiting Fine- and Coarse-Grained Parallelism Using a Directive Based Approach.
Proceedings of the OpenMP: Heterogenous Execution and Data Movements, 2015

Towards Task-Parallel Reductions in OpenMP.
Proceedings of the OpenMP: Heterogenous Execution and Data Movements, 2015

2014
Coordinating GPU threads for OpenMP 4.0 in LLVM.
Proceedings of the 2014 LLVM Compiler Infrastructure in HPC, 2014

Author retrospective for optimum modulo schedules for minimum register requirements.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

2013
Experimenting with low-overhead OpenMP runtime on IBM Blue Gene/Q.
IBM J. Res. Dev., 2013

OMPT: An OpenMP Tools Application Programming Interface for Performance Analysis.
Proceedings of the OpenMP in the Era of Low Power Devices and Accelerators, 2013

2012
The Design of OpenMP Thread Affinity.
Proceedings of the OpenMP in a Heterogeneous World - 8th International Workshop on OpenMP, 2012

2010
Automatic creation of tile size selection models.
Proceedings of the CGO 2010, 2010

2009
Compact multi-dimensional kernel extraction for register tiling.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2009

Exploiting Parallelism with Dependence-Aware Scheduling.
Proceedings of the PACT 2009, 2009

2008
Hybrid access-specific software cache techniques for the cell BE architecture.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2006
Using advanced compiler technology to exploit the performance of the Cell Broadband Engine<sup>TM</sup> architecture.
IBM Syst. J., 2006

2005
An integrated simdization framework using virtual vectors.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Efficient SIMD Code Generation for Runtime Alignment and Length Conversion.
Proceedings of the 3nd IEEE / ACM International Symposium on Code Generation and Optimization (CGO 2005), 2005

Optimizing Compiler for the CELL Processor.
Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT 2005), 2005

2004
Vectorization for SIMD architectures with alignment constraints.
Proceedings of the ACM SIGPLAN 2004 Conference on Programming Language Design and Implementation 2004, 2004

2002
Lower bounds on precedence-constrained scheduling for parallel processors.
Inf. Process. Lett., 2002

An Experimental Study of Algorithms for Weighted Completion Time Scheduling.
Algorithmica, 2002

2001
Scheduling Superblocks with Bound-Based Branch Trade-Offs.
IEEE Trans. Computers, 2001

2000
An integrated approach to accelerate data and predicate computations in hyperblocks.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

1999
Algorithms for Total Weighted Completion Time Scheduling.
Proceedings of the Tenth Annual ACM-SIAM Symposium on Discrete Algorithms, 1999

Balance Scheduling: Weighting Branch Tradeoffs in Superblocks.
Proceedings of the 32nd Annual IEEE/ACM International Symposium on Microarchitecture, 1999

1998
Effective Cluster Assignment for Modulo Scheduling.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998

Efficient Edge Profiling for ILP-Processors.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997
Efficient Formulation for Optimal Modulo Schedulers.
Proceedings of the ACM SIGPLAN '97 Conference on Programming Language Design and Implementation (PLDI), 1997

1996
Modulo scheduling, machine representations, and register-sensitive algorithms.
PhD thesis, 1996

Minimizing Register Requirements of a Modulo Schedule via Optimum Stage Scheduling.
Int. J. Parallel Program., 1996

A Reduced Multipipeline Machine Description that Preserves Scheduling Constraints.
Proceedings of the ACM SIGPLAN'96 Conference on Programming Language Design and Implementation (PLDI), 1996

1995
Stage scheduling: a technique to reduce the register requirements of a modulo schedule.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Register allocation for predicated code.
Proceedings of the 28th Annual International Symposium on Microarchitecture, Ann Arbor, Michigan, USA, November 29, 1995

Optimum Modulo Schedules for Minimum Register Requirements.
Proceedings of the 9th international conference on Supercomputing, 1995

Impact of Load Imbalance on the Design of Software Barriers.
Proceedings of the 1995 International Conference on Parallel Processing, 1995

Modeling load imbalance and fuzzy barriers for scalable shared-memory multiprocessors.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994
Minimum register requirements for a modulo schedule.
Proceedings of the 27th Annual International Symposium on Microarchitecture, San Jose, California, USA, November 30, 1994


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