Ulrich Kleine

According to our database1, Ulrich Kleine authored at least 26 papers between 1989 and 2009.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2009
Design of a complementary folded-cascode operational amplifier.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2007
Design of a Linear Power Amplifier with +/-1.5V Power Supply Using ALADIN.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2006
An automated design tool for analog layouts.
IEEE Trans. Very Large Scale Integr. Syst., 2006

Placement Algorithm in Analog-Layout Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

2005
A hybrid evolutionary analogue module placement algorithm for integrated circuit layout designs.
Int. J. Circuit Theory Appl., 2005

Macro-cell placement for analog physical designs using a hybrid genetic algorithm with simulated annealing.
Integr. Comput. Aided Eng., 2005

2004
A programmable inductive position sensor interface circuit.
Integr., 2004

A novel analog layout synthesis tool.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002
A novel class of complementary folded-cascode opamps for low voltage.
IEEE J. Solid State Circuits, 2002

A genetic approach to analog module placement with simulated annealing.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Mismatch optimization for analog circuits using the DesignAssistant.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A novel algorithm for detection of rapid approaching objects.
Proceedings of the IEEE International Conference on Acoustics, 2002

2001
An efficient and precise design method to optimize device areas in mismatch and flicker-noise sensitive analog circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000
A new design rule description for automated layout tools.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

Area Optimization of Analog Circuits Considering Matching Constraints.
Proceedings of the 2000 Design, 2000

1999
Reliability driven module generation for analog layouts.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1998
A low voltage differential OpAmp with novel common mode feedback.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Low-voltage medium Q-SC filters for high frequency communication applications.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

Automatic Topology Optimization for Analog Module Generators.
Proceedings of the 1998 Design, 1998

A Novel Design Assistant for Analog Circuits.
Proceedings of the ASP-DAC '98, 1998

1997
Application independent module generation in analog layouts.
Proceedings of the European Design and Test Conference, 1997

1996
Large bandwidth BiCMOS operational amplifiers for SC video applications.
IEEE J. Solid State Circuits, 1996

A Novel Analog Module Generator Environment.
Proceedings of the 1996 European Design and Test Conference, 1996

1995
Symbolic pole/zero calculation using SANTAFE.
IEEE J. Solid State Circuits, July, 1995

1994
A low-noise CMOS preamplifier operating at 4.2 K.
IEEE J. Solid State Circuits, August, 1994

1989
Two-dimensional FIR filter architectures based on NTT.
Proceedings of the IEEE International Conference on Acoustics, 1989


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