Vahid Janfaza

Orcid: 0000-0002-8656-4848

According to our database1, Vahid Janfaza authored at least 19 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Machine Learning, Deep Learning and Data Preprocessing Techniques for Detection, Prediction, and Monitoring of Stress and Stress-related Mental Disorders: A Scoping Review.
CoRR, 2023

Adaptive Gradient Prediction for DNN Training.
CoRR, 2023

Large Language Models Based Automatic Synthesis of Software Specifications.
CoRR, 2023

SmartIndex: Learning to Index Caches to Improve Performance.
IEEE Comput. Archit. Lett., 2023

ADA-GP: Accelerating DNN Training By Adaptive Gradient Prediction.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

MERCURY: Accelerating DNN Training By Exploiting Input Similarity.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

Post-Silicon Customization Using Deep Neural Networks.
Proceedings of the Architecture of Computing Systems - 36th International Conference, 2023

2022
An Automatic System to Monitor the Physical Distance and Face Mask Wearing of Construction Workers in COVID-19 Pandemic.
SN Comput. Sci., 2022

2021
SIMCNN - Exploiting Computational Similarity to Accelerate CNN Training in Hardware.
CoRR, 2021

OpenSync: An opensource platform for synchronizing multiple measures in neuroscience experiments.
CoRR, 2021

Localization, Mapping, Navigation, and Inspection Methods in In-Pipe Robots: A Review.
IEEE Access, 2021

Smart Navigation for an In-pipe Robot Through Multi-phase Motion Control and Particle Filtering Method.
Proceedings of the IEEE International Conference on Electro Information Technology, 2021

2017
A novel SAT-based ATPG approach for transition delay faults.
Proceedings of the 2017 IEEE International High Level Design Validation and Test Workshop, 2017

Hybrid history-based test, utilizing a probabilistic approach to reduce test time.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

A new fault-tolerant deadlock-free fully adaptive routing in NOC.
Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

2014
A Low-Power Enhanced Bitmask-Dictionary Scheme for Test Data Compression.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A mathematical model for estimating acceptable ratio of test patterns.
Proceedings of the 2014 East-West Design & Test Symposium, 2014

2013
Extracting complete set of equations to analyze VHDL-AMS descriptions.
Proceedings of the East-West Design & Test Symposium, 2013

Hybrid history-based test overlapping to reduce test application time.
Proceedings of the East-West Design & Test Symposium, 2013


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