Vaibhav Verma
Orcid: 0000-0001-9403-6319
According to our database1,
Vaibhav Verma
authored at least 12 papers
between 2014 and 2023.
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Bibliography
2023
LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Design Space Exploration of Layer-Wise Mixed-Precision Quantization with Tightly Integrated Edge Inference Units.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023
2022
EXTREM-EDGE - EXtensions To RISC-V for Energy-efficient ML inference at the EDGE of IoT.
Sustain. Comput. Informatics Syst., 2022
2021
Proceedings of the 7th IEEE World Forum on Internet of Things, 2021
2020
Comparative Analysis and Implementation of Single-ended Sense Amplifier Schemes using 65nm LSTP CMOS Technology.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020
2019
A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing.
IEEE Comput. Archit. Lett., 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processors.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
J. Low Power Electron., 2017
2015
A 128-kb 10% power reduced 1T high density ROM with 0.56 ns access time using bitline edge sensing in sub 16nm bulk FinFET technology.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015
2014
A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write Assist.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014