Sergiu Mosanu

Orcid: 0000-0003-0660-8036

According to our database1, Sergiu Mosanu authored at least 10 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2023
LiteAIR5: A System-Level Framework for the Design and Modeling of AI-extended RISC-V Cores.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023

Virtualized Controller for Computational RFID-based IoT Sensors.
Proceedings of the IEEE International Conference on RFID, 2023

FreezeTime: Towards System Emulation through Architectural Virtualization.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

FreezeTime: Towards System Emulation through Architectural Virtualization.
Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

2022
Agile-AES: Implementation of configurable AES primitive with agile design approach.
Integr., 2022

RECO-HCON: A High-Throughput Reconfigurable Compact ASCON Processor for Trusted IoT.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

PiMulator: a Fast and Flexible Processing-in-Memory Emulation Platform.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2020
Micro - GAGE: A Low-power Compact GAGE Hash Function Processor for IoT Applications.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019
Flexi-AES: A Highly-Parameterizable Cipher for a Wide Range of Design Constraints.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

2017
Back to the Future: Digital Circuit Design in the FinFET Era.
J. Low Power Electron., 2017


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