Vanchinathan Venkataramani

Orcid: 0000-0002-0259-6456

According to our database1, Vanchinathan Venkataramani authored at least 17 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
ASCENT: Communication Scheduling for SDF on Bufferless Software-Defined NoC.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

2020
SPECTRUM: A Software-defined Predictable Many-core Architecture for LTE/5G Baseband Processing.
ACM Trans. Embed. Comput. Syst., 2020

Simultaneous Progressing Switching Protocols for Timing Predictable Real-Time Network-on-Chips.
Proceedings of the 26th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2020

Time-Predictable Software-Defined Architecture with Sdf-Based Compiler Flow for 5g Baseband Processing.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

Unified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-Cores.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Scratchpad-Memory Management for Multi-Threaded Applications on Many-Core Architectures.
ACM Trans. Embed. Comput. Syst., 2019

Scalable Optimal Greedy Scheduler for Asymmetric Multi-/Many-Core Processors.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019

SPECTRUM: a software defined predictable many-core architecture for LTE baseband processing.
Proceedings of the 20th ACM SIGPLAN/SIGBED International Conference on Languages, 2019

2018
LOCUS: Low-Power Customizable Many-Core Architecture for Wearables.
ACM Trans. Embed. Comput. Syst., 2018

Scalable Dynamic Task Scheduling on Adaptive Many-Core.
Proceedings of the 12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2018

2017
Optimal Greedy Algorithm for Many-Core Scheduling.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Defragmentation of Tasks in Many-Core Architecture.
ACM Trans. Archit. Code Optim., 2017

2016
Distributed fair scheduling for many-cores.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Distributed scheduling for many-cores using cooperative game theory.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2014
Design space exploration of multiple loops on FPGAs using high level synthesis.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
Hierarchical power management for asymmetric multi-core in dark silicon era.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Power-performance modeling on asymmetric multi-cores.
Proceedings of the International Conference on Compilers, 2013


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