Guanwen Zhong

According to our database, Guanwen Zhong authored at least 11 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

A Primer on RecoNIC: RDMA-enabled Compute Offloading on SmartNIC.

Guanwen Zhong, Aditya Kolekar, Burin Amornpaisannon, Inho Choi, Haris Javaid, Mario Baldi

CoRR, 2023

2019

Synergy: An HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC.

Guanwen Zhong, Akshat Dubey, Cheng Tan, Tulika Mitra

ACM Trans. Embed. Comput. Syst., 2019

FastProxy: Hardware and Software Acceleration of Stratum Mining Proxy.

Guanwen Zhong, Haris Javaid, Hassaan Saadat, Lingchao Xu, Chengchen Hu, Gordon J. Brebner

Proceedings of the Crypto Valley Conference on Blockchain Technology, 2019

2018

Synergy: A HW/SW Framework for High Throughput CNNs on Embedded Heterogeneous SoC.

Guanwen Zhong, Akshat Dubey, Cheng Tan, Tulika Mitra

CoRR, 2018

2017

CGPredict: Embedded GPU Performance Estimation from Single-Threaded Applications.

Siqi Wang, Guanwen Zhong, Tulika Mitra

ACM Trans. Embed. Comput. Syst., 2017

A Rapid Data Communication Exploration Tool for Hybrid CPU-FPGA Architectures.

Mariem Makni, Smaïl Niar, Mouna Baklouti, Guanwen Zhong, Tulika Mitra, Mohamed Abid

Proceedings of the 25th Euromicro International Conference on Parallel, 2017

Design Space exploration of FPGA-based accelerators with multi-level parallelism.

Guanwen Zhong, Alok Prakash, Siqi Wang, Yun Liang, Tulika Mitra, Smaïl Niar

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016

Design of Multiple-Target Tracking System on Heterogeneous System-on-Chip Devices.

Guanwen Zhong, Smaïl Niar, Alok Prakash, Tulika Mitra

IEEE Trans. Veh. Technol., 2016

Lin-analyzer: a high-level performance analysis tool for FPGA-based accelerators.

Guanwen Zhong, Alok Prakash, Yun Liang, Tulika Mitra, Smaïl Niar

Proceedings of the 53rd Annual Design Automation Conference, 2016

2014

Design space exploration of multiple loops on FPGAs using high level synthesis.

Guanwen Zhong, Vanchinathan Venkataramani, Yun Liang, Tulika Mitra, Smaïl Niar

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2011

1024-point pipeline FFT processor with pointer FIFOs based on FPGA.

Guanwen Zhong, Hongbin Zheng, ZhenHua Jin, Dihu Chen, Zhiyong Pang

Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011