Venkat Abilash Reddy Nerallapally

According to our database, Venkat Abilash Reddy Nerallapally authored at least 3 papers between 2017 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency.

Milind Sonawane, Venkat Abilash Reddy Nerallapally, Alex Hsu, Shantanu Sarangi

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms.

Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2017

At-speed capture global noise reduction & low-power memory test architecture.

Bonita Bhaskaran, Sailendra Chadalavada, Shantanu Sarangi, Nithin Valentine, Venkat Abilash Reddy Nerallapally, Ayub Abdollahian

Proceedings of the 35th IEEE VLSI Test Symposium, 2017