Sailendra Chadalavada

According to our database, Sailendra Chadalavada authored at least 6 papers between 2016 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

Next-Gen Scalable In-System-Test Architecture for Nvidia Automotive Platform.

Sailendra Chadalavada, Milind Sonawane, Saranyan Sarangan, Alex Hsu, Pavan Javvaji, Shantanu Sarangi

Proceedings of the 44th IEEE VLSI Test Symposium, 2026

2019

Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms.

Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Shashank Bajpai, Venkat Abilash Reddy Nerallapally, Jayesh Pandey, Sam Jiang

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2017

At-speed capture global noise reduction & low-power memory test architecture.

Bonita Bhaskaran, Sailendra Chadalavada, Shantanu Sarangi, Nithin Valentine, Venkat Abilash Reddy Nerallapally, Ayub Abdollahian

Proceedings of the 35th IEEE VLSI Test Symposium, 2017

2016

Dynamic docking architecture for concurrent testing and peak power reduction.

Milind Sonawane, Pavan Kumar Datla Jagannadha, Sailendra Chadalavada, Shantanu Sarangi, Mahmut Yilmaz, Amit Sanghani, Karthikeyan Natarajan, Jonathon E. Colburn, Anubhav Sinha

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Flexible scan interface architecture for complex SoCs.

Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Amit Sanghani, Mahmut Yilmaz, Pavan Kumar Datla Jagannadha, Jonathon E. Colburn

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Advanced test methodology for complex SoCs.

Pavan Kumar Datla Jagannadha, Mahmut Yilmaz, Milind Sonawane, Sailendra Chadalavada, Shantanu Sarangi, Bonita Bhaskaran, Ayub Abdollahian

Proceedings of the 2016 IEEE International Test Conference, 2016