Milind Sonawane

According to our database1, Milind Sonawane authored at least 8 papers between 2014 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Next-Gen Scalable In-System-Test Architecture for Nvidia Automotive Platform.
Proceedings of the 44th IEEE VLSI Test Symposium, 2026

2022
NVIDIA MATHS: Mechanism to Access Test-Data over High-Speed Links.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022

2019
Hybrid Performance Modeling for Optimization of In-System-Structural-Test (ISST) Latency.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Special Session: In-System-Test (IST) Architecture for NVIDIA Drive-AGX Platforms.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

2016
Dynamic docking architecture for concurrent testing and peak power reduction.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Flexible scan interface architecture for complex SoCs.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Advanced test methodology for complex SoCs.
Proceedings of the 2016 IEEE International Test Conference, 2016

2014
Achieving extreme scan compression for SoC Designs.
Proceedings of the 2014 International Test Conference, 2014


  Loading...