Victor Perrin

According to our database, Victor Perrin authored at least 3 papers between 2019 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

A 16nm 140-fJ/b/dB Dual-Mode ENRZ/NRZ Serial Data Transceiver with Dynamic Voltage Scaling.

Armin Tajalli, Cosimo Aprile, Milad Ataei, Rolf Beerwerth, Dario Carneli, Maik Fuhs, Kiarash Gharibdoust, Ali Hormati, James Hudner, Victor Perrin, Amin Shokrollahi, Richard Simpson, Andrew Stewart, David Stauffer, Giuseppe Surace, Roger Ulrich, Patrick Urban, Mark Venneborger, Anant Singh

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2020

A 1.02-pJ/b 20.83-Gb/s/Wire USR Transceiver Using CNRZ-5 in 16-nm FinFET.

Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh

IEEE J. Solid State Circuits, 2020

2019

A 1.02pJ/b 417Gb/s/mm USR Link in 16nm FinFET.

Armin Tajalli, Mani Bastani Parizi, Dario Albino Carnelli, Chen Cao, John Fox, Kiarash Gharibdoust, Davide Gorret, Amit Gupta, Christopher Hall, Ahmed Hassanin, Klaas L. Hofstra, Brian Holden, Ali Hormati, John Keay, Yohann Mogentale, G. Paul, Victor Perrin, John Phillips, Sumathi Raparthy, Amin Shokrollahi, David Stauffer, Richard Simpson, Andrew Stewart, Giuseppe Surace, Omid Talebi Amiri, Emanuele Truffa, Anton Tschank, Roger Ulrich, Christoph Walter, Anant Singh

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019