Cosimo Aprile
Orcid: 0000-0002-6558-7688
According to our database1,
Cosimo Aprile
authored at least 16 papers
between 2015 and 2022.
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Bibliography
2022
A 16-Channel Neural Recording System-on-Chip With CHT Feature Extraction Processor in 65-nm CMOS.
IEEE J. Solid State Circuits, 2022
2021
A 16-Channel Wireless Neural Recording System-on-Chip with CHT Feature Extraction Processor in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021
2020
A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET.
IEEE J. Solid State Circuits, 2020
2019
A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
A 4.8pJ/b 56Gb/s ADC-Based PAM-4 Wireline Receiver Data-Path with Cyclic Prefix in 14nm FinFET.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels.
IEEE J. Solid State Circuits, 2018
Parallel Implementation Technique of Digital Equalizer for Ultra-High-Speed Wireline Receiver.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 26th European Signal Processing Conference, 2018
An area and power efficient on-the-fly LBCS transformation for implantable neuronal signal acquisition systems.
Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018
2017
Proceedings of the Computing Frontiers Conference, 2017
2016
Learning-Based Near-Optimal Area-Power Trade-offs in Hardware Design for Neural Signal Acquisition.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
2015
A 5.9mW/Gb/s 7Gb/s/pin 8-lane single-ended RX with crosstalk cancellation scheme using a XCTLE and 56-tap XDFE in 32nm SOI CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 23rd European Signal Processing Conference, 2015
Proceedings of the 6th IEEE International Workshop on Computational Advances in Multi-Sensor Adaptive Processing, 2015