Vijay Degalahal

According to our database1, Vijay Degalahal authored at least 14 papers between 2002 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
Compiler-assisted soft error detection under performance and energy constraints in embedded systems.
ACM Trans. Embed. Comput. Syst., 2009

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.
IEEE Trans. Dependable Secur. Comput., 2009

2007
Compiler-Directed Code Restructuring for Operating with Compressed Arrays.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Enhancing Locality in Two-Dimensional Space through Integrated Computation and Data Mappings.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2006
A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

2005
Soft errors issues in low-power caches.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Compiler-Directed Instruction Duplication for Soft Error Detection.
Proceedings of the 2005 Design, 2005

Methodology for high level estimation of FPGA power consumption.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Reducing instruction cache energy consumption using a compiler-based strategy.
ACM Trans. Archit. Code Optim., 2004

The Effect of Threshold Voltages on the Soft Error Rate.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Soft error and energy consumption interactions: a data cache perspective.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

2003
Analyzing Soft Errors in Leakage Optimized SRAM Design.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Effect of Power Optimizations on Soft Error Rate.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

2002
Compiler-directed instruction cache leakage optimization.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002


  Loading...