Rajaraman Ramanarayanan

According to our database, Rajaraman Ramanarayanan authored at least 11 papers between 2003 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2013

Split-Path Fused Floating Point Multiply Accumulate (FPMAC).

Suresh Srinivasan, Ketan Bhudiya, Rajaraman Ramanarayanan, P. Sahit Babu, Tiju Jacob, Sanu Mathew, Ram Krishnamurthy, Vasantha Erraguntla

Proceedings of the 21st IEEE Symposium on Computer Arithmetic, 2013

2012

A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS.

Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

An IA-32 processor with a wide voltage operating range in 32nm CMOS.

Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar

Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012

2010

A 320mV-to-1.2V on-die fine-grained reconfigurable fabric for DSP/media accelerators in 32nm CMOS.

Amit Agarwal, Sanu Mathew, Steven Hsu, Mark A. Anders, Himanshu Kaul, Farhana Sheikh, Rajaraman Ramanarayanan, Suresh Srinivasan, Ram Krishnamurthy, Shekhar Borkar

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

18Gbps, 50mW reconfigurable multi-mode SHA Hashing accelerator in 45nm CMOS.

Rajaraman Ramanarayanan, Sanu Mathew, Farhana Sheikh, Suresh Srinivasan, Amit Agarwal, Steven Hsu, Himanshu Kaul, Mark A. Anders, Vasantha Erraguntla, Ram Krishnamurthy

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.

Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu

IEEE Trans. Dependable Secur. Comput., 2009

2008

A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.

Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Locality-Aware Distributed Loop Scheduling for Chip Multiprocessors.

Liping Xue, Mahmut T. Kandemir, Guilin Chen, Feihui Li, Ozcan Ozturk, Rajaraman Ramanarayanan, Balaji Vaidyanathan

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Process Scheduler-Based Approach to NoC Power Management.

Feihui Li, Guilin Chen, Mahmut T. Kandemir, Ozcan Ozturk, Mustafa Karaköy, Rajaraman Ramanarayanan, Balaji Vaidyanathan

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

2004

The Effect of Threshold Voltages on the Soft Error Rate.

Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin

Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

2003

Effect of Power Optimizations on Soft Error Rate.

Vijay Degalahal, Rajaraman Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin

Proceedings of the VLSI-SOC: From Systems to Chips, 2003