Vipul J. Patel

According to our database1, Vipul J. Patel authored at least 6 papers between 2013 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A High Linearity, 2.8 GS/s, 10-bit Accurate, Sample and Hold Amplifier in 130 nm SiGe BiCMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR.
IEEE J. Solid State Circuits, 2017

2016
A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis.
IEEE J. Solid State Circuits, 2016

2013
InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR.
IEEE J. Solid State Circuits, 2013

Accuracy and speed limitations in DACs across CMOS process technologies.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013


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