Myung-Jun Choe

According to our database1, Myung-Jun Choe authored at least 7 papers between 2002 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR.
IEEE J. Solid State Circuits, 2017

16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2005
Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2003
An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002


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