Brian Dupaix

According to our database1, Brian Dupaix authored at least 15 papers between 2014 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Vulnerabilities and Reliability of ReRAM Based PUFs and Memory Logic.
IEEE Trans. Reliab., 2020

2019
Wide-Bandwidth, High-Linearity, 2.8-GS/s, 10-bit Accurate Sample and Hold Amplifier in 130-nm SiGe BiCMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Process Specific Functions for Assurance of Analog/Mixed-Signal Integrated Circuits.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver.
IEEE J. Solid State Circuits, 2018

Sense amplifier offset cancellation and replica timing calibration for high-speed SRAMs.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

An on-chip resonant-gate-drive switched-capacitor converter for near-threshold computing achieving 70.2% efficiency at 0.92A/mm<sup>2</sup> current density and 0.4V output.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A High Linearity, 2.8 GS/s, 10-bit Accurate, Sample and Hold Amplifier in 130 nm SiGe BiCMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR.
IEEE J. Solid State Circuits, 2017

16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

A calibration-free low-power supply-pushing reduction circuit (SPRC) for LC VCOs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis.
IEEE J. Solid State Circuits, 2016

2015
A fully-integrated switched capacitor voltage regulator for near-threshold applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Tracking energy efficiency of near-threshold design using process variation control techniques.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

On the design of RF-DACs for random acquisition based reconfigurable receivers.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014


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