Jamin J. McCue

Orcid: 0000-0002-2896-3429

According to our database1, Jamin J. McCue authored at least 10 papers between 2011 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2019
Analysis of SRAM Enhancements Through Sense Amplifier Capacitive Offset Correction and Replica Self-Timing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A Capacitively Coupled, Pseudo Return-to-Zero Input, Latched-Bias Data Receiver.
IEEE J. Solid State Circuits, 2018

2017
A 10-bit DC-20-GHz Multiple-Return-to-Zero DAC With >48-dB SFDR.
IEEE J. Solid State Circuits, 2017

16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDR.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
A Time-Interleaved Multimode ΔΣ RF-DAC for Direct Digital-to-RF Synthesis.
IEEE J. Solid State Circuits, 2016

2014
On the design of RF-DACs for random acquisition based reconfigurable receivers.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
Frequency Tuning Range Extension in LC-VCOs Using Negative-Capacitance Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 10mW 37.8GHz current-redistribution BiCMOS VCO with an average FOMT of -193.5dBc/Hz.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Analytical and experimental study of tuning range limitation in mm-wave CMOS LC-VCOs.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2011
Systematic Analysis of Interleaved Digital-to-Analog Converters.
IEEE Trans. Circuits Syst. II Express Briefs, 2011


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