Jean-François Nezan
Orcid: 0000-0002-0609-4592
According to our database1,
Jean-François Nezan
authored at least 84 papers
between 2002 and 2024.
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Bibliography
2024
ACM Trans. Reconfigurable Technol. Syst., March, 2024
2023
OpenVVC Decoder Parameterized and Interfaced Synchronous Dataflow (PiSDF) Model: Tile Based Parallelism.
J. Signal Process. Syst., July, 2023
Automated Clustering and Pipelining of Dataflow Actors for Controlled Scheduling Complexity.
Proceedings of the 31st European Signal Processing Conference, 2023
Proceedings of the Design and Architecture for Signal and Image Processing, 2023
2022
Multiple Transform Selection Concept Modeling and Implementation Using Dynamic and Parameterized Dataflow Graphs.
J. Signal Process. Syst., 2022
Proceedings of the Design and Architecture for Signal and Image Processing, 2022
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022
2021
Multiple Transform Selection concept modeling and implementation using Interface Based SDF graphs.
Proceedings of the DASIP '21: Workshop on Design and Architectures for Signal and Image Processing (14th edition), 2021
2020
Forward-Inverse 2D Hardware Implementation of Approximate Transform Core for the VVC Standard.
IEEE Trans. Circuits Syst. Video Technol., 2020
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020
Scheduling of Synchronous Dataflow Graphs with Partially Periodic Real-Time Constraints.
Proceedings of the 28th International Conference on Real Time Networks and Systems, 2020
2019
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2019
Hardware Acceleration of Approximate Transform Module for the Versatile Video Coding Standard.
Proceedings of the 27th European Signal Processing Conference, 2019
2018
Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard.
IEEE Trans. Consumer Electron., 2018
Reproducible Evaluation of System Efficiency With a Model of Architecture: From Theory to Practice.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
A Distributed Framework for Low-Latency OpenVX over the RDMA NoC of a Clustered Manycore.
Proceedings of the 2018 IEEE High Performance Extreme Computing Conference, 2018
Proceedings of the 9th Workshop on Parallel Programming and RunTime Management Techniques for Manycore Architectures and 7th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2018
An optimized hardware implementation of 4-point adaptive multiple transform design for post-HEVC.
Proceedings of the 4th International Conference on Advanced Technologies for Signal and Image Processing, 2018
2017
J. Syst. Archit., 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Hierarchical Dataflow Model for efficient programming of clustered manycore processors.
Proceedings of the 28th IEEE International Conference on Application-specific Systems, 2017
A comparison of stereo matching algorithms on multi-core Digital Signal Processor platform.
Proceedings of the 3D Image Processing, Measurement (3DIPM), and Applications 2017, Burlingame, CA, USA, January 29, 2017
2016
Scheduling of Parallelized Synchronous Dataflow Actors for Multicore Signal Processing.
J. Signal Process. Syst., 2016
ACM Trans. Embed. Comput. Syst., 2016
Models of Architecture: Reproducible Efficiency Evaluation for Signal Processing Systems.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Optimized Belief Propagation Algorithm onto Embedded Multi and Many-Core Systems for Stereo Matching.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
2015
Memory Analysis and Optimized Allocation of Dataflow Applications on Shared-Memory MPSoCs - In-Depth Study of a Computer Vision Application.
J. Signal Process. Syst., 2015
Buffer merging technique for minimizing memory footprints of Synchronous Dataflow specifications.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014
Optimized fixed point implementation of a local stereo matching algorithm onto C66x DSP.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Demonstrating a dataflow-based RTOS for heterogeneous MPSoC by means of a stereo matching application.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
2013
Lecture Notes in Electrical Engineering 171, Springer, ISBN: 978-1-4471-4209-6, 2013
PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfiguration.
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
Proceedings of the 2013 International Symposium on System on Chip, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
Applying the adaptive Hybrid Flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors.
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
An efficient Resource Management to optimize the placement of hardware task on FPGA in the RVC framework.
Des. Autom. Embed. Syst., 2012
Memory bounds for the distributed execution of a hierarchical Synchronous Data-Flow graph.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Implementation of stereo matching using a high level compiler for parallel computing acceleration.
Proceedings of the Image and Vision Computing New Zealand, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Implementation of Motion Estimation Based on Heterogeneous Parallel Computing System with OpenCL.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
A hierarchical implementation of Hadamard transform using RVC-CAL dataflow programming and dynamic partial reconfiguration.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
FPGA dynamic reconfiguration using the RVC technology: Inverse quantization case study.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011
2010
Advanced list scheduling heuristic for task scheduling with communication contention for parallel embedded systems.
Sci. China Inf. Sci., 2010
Proceedings of the Mobile Multimedia Communications - 6th International ICST Conference, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010
2009
HDS, a real-time multi-DSP motion estimator for MPEG-4 H.264 AVC high definition video encoding.
J. Real Time Image Process., 2009
EURASIP J. Embed. Syst., 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Prototypage rapide d'applications de traitement des images sur systèmes embarqués. (Rapid prototyping of image processing applications on embedded systems).
, 2009
2008
A Flexible Heterogeneous Hardware/Software Solution for Real-Time HD H.264 Motion Estimation.
IEEE Trans. Circuits Syst. Video Technol., 2008
Optimization of automatically generated multi-core code for the LTE RACH-PD algorithm
CoRR, 2008
Code generation for the MPEG Reconfigurable Video Coding framework: From CAL actions to C functions.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008
Proceedings of the International Conference on Image Processing, 2008
2007
H.264 fractional motion estimation refinement: A real-time and low complexity hardware solution forhd sequences.
Proceedings of the 15th European Signal Processing Conference, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
2006
EURASIP J. Embed. Syst., 2006
Rapid Prototyping for Heterogeneous Multicomponent Systems: An MPEG-4 Stream over a UMTS Communication Link.
EURASIP J. Adv. Signal Process., 2006
Automatic dsp cache memory management and fast prototyping for multiprocessor image applications.
Proceedings of the 14th European Signal Processing Conference, 2006
Proceedings of the 14th European Signal Processing Conference, 2006
2005
SynDEx executive kernels for fast developments of applications over heterogeneous architectures.
Proceedings of the 13th European Signal Processing Conference, 2005
2004
Fast Prototyping Methodology for Distributed and Heterogeneous Architectures: Application to Mpeg-4 Video Tools.
Des. Autom. Embed. Syst., 2004
2003
Rapid prototyping for an optimized MPEG4 decoder implementation over a parallel heterogeneous architecture.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003
Rapid prototyping for an optimized MPEG-4 decoder implementation over a parallel heterogenous architecture.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
2002
AVSynDEx: A Rapid Prototyping Process Dedicated to the Implementation of Digital Image Processing Applications on Multi-DSP and FPGA Architectures.
EURASIP J. Adv. Signal Process., 2002
Rapid prototyping methodology for multi-DSP TI C6X platforms applied to an Mpeg-2 coding application.
Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2002
A VsynDEx Methodology for Fast Prototyping of Multi-C6x DSP Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002
Syndex executive kernel development for DSPs TI C6X applied to real-time and embedded multiprocessors architectures.
Proceedings of the 11th European Signal Processing Conference, 2002