Mickaël Raulet

According to our database1, Mickaël Raulet authored at least 91 papers between 2002 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
4K Real Time Software Solution of Scalable HEVC for Broadcast Video Application.
IEEE Access, 2019

Decoder-Side Intra Mode Derivation Based on a Histogram of Gradients in Versatile Video Coding.
Proceedings of the Data Compression Conference, 2019

2018
Efficient System-Level Hardware Synthesis of Dataflow Programs Using Shared Memory Based FIFO - HEVC Decoder Case Study.
Signal Processing Systems, 2018

2017
On the Development and Optimization of HEVC Video Decoders Using High-Level Dataflow Modeling.
Signal Processing Systems, 2017

Efficient parallel architecture for a real-time UHD scalable HEVC encoder.
Proceedings of the 25th European Signal Processing Conference, 2017

2016
4K Real-Time and Parallel Software Video Decoder for Multilayer HEVC Extensions.
IEEE Trans. Circuits Syst. Video Techn., 2016

Real-time UHD scalable multi-layer HEVC encoder architecture.
Proceedings of the 24th European Signal Processing Conference, 2016

Demo: UHD live video streaming with a real-time scalable HEVC encoder.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

Efficient parallel architecture of an intra-only scalable multi-layer HEVC encoder.
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

2015
Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs.
Signal Processing Systems, 2015

Energy estimation models for video decoders: reconfigurable video coding-CAL case-study.
IET Computers & Digital Techniques, 2015

Selective video encryption using chaotic system in the SHVC extension.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015

2014
Energy-aware decoder management: a case study on RVC-CAL specification based on just-in-time adaptive decoder engine.
IEEE Trans. Consumer Electronics, 2014

Ultra high definition HEVC DASH data set.
Proceedings of the Multimedia Systems Conference 2014, 2014

Parallel SHVC decoder: Implementation and analysis.
Proceedings of the IEEE International Conference on Multimedia and Expo, 2014

4K real time video streaming with SHVC decoder and GPAC player.
Proceedings of the 2013 IEEE International Conference on Multimedia and Expo Workshops, 2014

Unified real time software decoder for HEVC extensions.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Real time SHVC decoder: Implementation and complexity analysis.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

On-line energy estimation model of an RVC-CAL HEVC decoder.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

A DSP HEVC decoder implementation based on OpenHEVC.
Proceedings of the IEEE International Conference on Consumer Electronics, 2014

Efficient software synthesis of dynamic dataflow programs.
Proceedings of the IEEE International Conference on Acoustics, 2014

Multi-core software architecture for the scalable HEVC decoder.
Proceedings of the IEEE International Conference on Acoustics, 2014

Efficient quantization parameter estimation in HEVC based on ρ-domain.
Proceedings of the 22nd European Signal Processing Conference, 2014

Energy-aware decoders: A case study based on an RVC-CAL specification.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Orcc's compa-backend demonstration.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014

Development and optimization of high level dataflow programs: The HEVC decoder design case.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
Automatic Hierarchical Discovery of Quasi-Static Schedules of RVC-CAL Dataflow Programs.
Signal Processing Systems, 2013

A DSP-Based HEVC decoder implementation using an actor language dataflow model.
IEEE Trans. Consumer Electronics, 2013

Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs.
Sig. Proc.: Image Comm., 2013

Special issue on MPEG CCF.
Sig. Proc.: Image Comm., 2013

Reconfigurable media coding: An overview.
Sig. Proc.: Image Comm., 2013

MPEG Reconfigurable Video Coding: From specification to a reconfigurable implementation.
Sig. Proc.: Image Comm., 2013

Optimized dynamic compilation of dataflow representations for multimedia applications.
Annales des Télécommunications, 2013

Orcc: multimedia development made easy.
Proceedings of the ACM Multimedia Conference, 2013

Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms.
Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Comparison of different parallel implementations for deblocking filter of HEVC.
Proceedings of the IEEE International Conference on Acoustics, 2013

Efficient Parallelization of Different HEVC Decoding Stages.
Proceedings of the 2013 Data Compression Conference, 2013

System-level PMC-driven energy estimation models in RVC-CAL video codec specifications.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Automatic Generation of Optimized and Synthesizable Hardware Implementation from High-Level Dataflow Programs.
VLSI Design, 2012

Classification of Dataflow Actors with Satisfiability and Abstract Interpretation.
IJERTCS, 2012

Automatic generation of synthesizable hardware implementation from high level RVC-cal description.
Proceedings of the 2012 IEEE International Conference on Acoustics, 2012

An experimental toolchain based on high-level dataflow models of computation for heterogeneous MPSoC.
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2011
Guest Editorial: Special Issue on Reconfigurable Video Coding.
Signal Processing Systems, 2011

Synthesizing Hardware from Dataflow Programs - An MPEG-4 Simple Profile Decoder Case Study.
Signal Processing Systems, 2011

Exploiting Statically Schedulable Regions in Dataflow Programs.
Signal Processing Systems, 2011

Overview of the MPEG Reconfigurable Video Coding Framework.
Signal Processing Systems, 2011

A DSP based H.264/SVCdecoder for a multimedia terminal.
IEEE Trans. Consumer Electronics, 2011

LLVM-based and scalable MPEG-RVC decoder.
J. Real-Time Image Processing, 2011

Efficient multicore scheduling of dataflow process networks.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Just-in-time adaptive decoder engine: a universal video decoder based on MPEG RVC.
Proceedings of the 19th International Conference on Multimedia 2011, Scottsdale, AZ, USA, November 28, 2011

Scheduling of CAL actor networks based on dynamic code analysis.
Proceedings of the IEEE International Conference on Acoustics, 2011

Interfacing and scheduling legacy code within the Canals framework.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

A unified hardware/software co-synthesis solution for signal processing systems.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010
The Reconfigurable Video Coding Standard [Standards in a Nutshell].
IEEE Signal Process. Mag., 2010

Advanced list scheduling heuristic for task scheduling with communication contention for parallel embedded systems.
SCIENCE CHINA Information Sciences, 2010

Overview of the SVC4QoE Project.
Proceedings of the Mobile Multimedia Communications - 6th International ICST Conference, 2010

Reconfigurable video coding: a stream programming approach to the specification of new video coding standards.
Proceedings of the First Annual ACM SIGMM Conference on Multimedia Systems, 2010

Open SVC decoder: a flexible SVC library.
Proceedings of the 18th International Conference on Multimedia 2010, 2010

A codesign synthesis from an MPEG-4 decoder dataflow description.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A Test Bench for Distortion-Energy Optimization of a DSP-Based H.264/SVC Decoder.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Classification and transformation of dynamic dataflow programs.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Automated generation of an efficient MPEG-4 Reconfigurable Video Coding decoder implementation.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

A portable Video Tool Library for MPEG Reconfigurable Video Coding using LLVM representation.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

RVC-CAL dataflow implementations of MPEG AVC/H.264 CABAC decoding.
Proceedings of the 2010 Conference on Design & Architectures for Signal & Image Processing, 2010

Loop transformations for interface-based hierarchies IN SDF graphs.
Proceedings of the 21st IEEE International Conference on Application-specific Systems Architectures and Processors, 2010

MPEG Reconfigurable Video Coding.
Proceedings of the Handbook of Signal Processing Systems, 2010

2009
Exploring the Concurrency of an MPEG RVC Decoder Based on Dataflow Program Analysis.
IEEE Trans. Circuits Syst. Video Techn., 2009

HDS, a real-time multi-DSP motion estimator for MPEG-4 H.264 AVC high definition video encoding.
J. Real-Time Image Processing, 2009

Interface-based hierarchy for synchronous data-flow graphs.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

An Integrated Environment for HW/SW Co-design based on a CAL Specification and HW/SW Code Generators.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

An RVC dataflow description of the AVC Constrained Baseline Profile decoder.
Proceedings of the International Conference on Image Processing, 2009

Exploiting statically schedulable regions in dataflow programs.
Proceedings of the IEEE International Conference on Acoustics, 2009

2008
OpenDF: a dataflow toolset for reconfigurable hardware and multicore systems.
SIGARCH Computer Architecture News, 2008

Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Validation of bitstream syntax and synthesis of parsers in the MPEG Reconfigurable Video Coding framework.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Code generation for the MPEG Reconfigurable Video Coding framework: From CAL actions to C functions.
Proceedings of the 2008 IEEE International Conference on Multimedia and Expo, 2008

Software synthesis of CAL actors for the MPEG reconfigurable Video Coding framework.
Proceedings of the International Conference on Image Processing, 2008

2007
Automatic code generation for multi-microblaze system with syndex.
Proceedings of the 15th European Signal Processing Conference, 2007

Framework for efficient cosimulation and fast prototyping on multi-components with AAA methodology: LAR codec study case.
Proceedings of the 15th European Signal Processing Conference, 2007

2006
Rapid Prototyping for Heterogeneous Multicomponent Systems: An MPEG-4 Stream over a UMTS Communication Link.
EURASIP J. Adv. Sig. Proc., 2006

Automatic dsp cache memory management and fast prototyping for multiprocessor image applications.
Proceedings of the 14th European Signal Processing Conference, 2006

Using RTOS in the AAA methodology automatic executive generation.
Proceedings of the 14th European Signal Processing Conference, 2006

2005
SynDEx executive kernels for fast developments of applications over heterogeneous architectures.
Proceedings of the 13th European Signal Processing Conference, 2005

2004
Fast Prototyping Methodology for Distributed and Heterogeneous Architectures: Application to Mpeg-4 Video Tools.
Design Autom. for Emb. Sys., 2004

2003
Rapid prototyping for an optimized MPEG4 decoder implementation over a parallel heterogeneous architecture.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Rapid prototyping for an optimized MPEG-4 decoder implementation over a parallel heterogenous architecture.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

2002
Rapid prototyping methodology for multi-DSP TI C6X platforms applied to an Mpeg-2 coding application.
Proceedings of the Fourteenth Annual ACM Symposium on Parallel Algorithms and Architectures, 2002

A VsynDEx Methodology for Fast Prototyping of Multi-C6x DSP Architectures.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002

Syndex executive kernel development for DSPs TI C6X applied to real-time and embedded multiprocessors architectures.
Proceedings of the 11th European Signal Processing Conference, 2002


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