Vitalij Ocheretnij

According to our database1, Vitalij Ocheretnij authored at least 16 papers between 2000 and 2006.

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Bibliography

2006
Modulo <i>p</i>=3 Checking for a Carry Select Adder.
J. Electron. Test., 2006

A New Self-Checking and Code-Disjoint Non-Restoring Array Divider.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005
On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-Box Implementations.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
A Signature Analysis Technique for the Identification of Failing Vectors with Application to Scan-BIST.
J. Electron. Test., 2004

Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder.
Proceedings of the 9th European Test Symposium, 2004

A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.
Proceedings of the 2004 Design, 2004

Self-checking Carry-selectAdder with Sum-bit Duplication.
Proceedings of the ARCS 2004, 2004

2003
A Modulo p Checked Self-Checking Carry Select Adder.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

2002
A New Self-Checking Code-Disjoint Carry-Skip Adder.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Partially Duplicated Code-Disjoint Carry-Skip Adder.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Diagnosis by Repeated Application of Specific Test Inputs and by Output Monitoring of the MISA.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
A New Method of Redundancy Addition for Circuit Optimization.
Proceedings of the 26th EUROMICRO 2000 Conference, 2000


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