Egor S. Sogomonyan

According to our database1, Egor S. Sogomonyan authored at least 36 papers between 1992 and 2020.

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Bibliography

2020
Full Error Detection and Correction Method Applied on Pipelined Structure Using Two Approaches.
J. Circuits Syst. Comput., 2020

2016
Enhanced architectures for soft error detection and correction in combinational and sequential circuits.
Microelectron. Reliab., 2016

2013
Error Correction of Transient Errors in a Sum-Bit Duplicated Adder by Error Detection.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A new method for correcting time and soft errors in combinational circuits.
Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2008
A Non-linear Split Error Detection Code.
Fundam. Informaticae, 2008

2006
Modulo <i>p</i>=3 Checking for a Carry Select Adder.
J. Electron. Test., 2006

A New Self-Checking and Code-Disjoint Non-Restoring Array Divider.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

On-line Fault Detection and Location for NoC Interconnects.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005
New Self-checking Output-Duplicated Booth Multiplier with High Fault Coverage for Soft Errors.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A new self-checking multiplier by use of a code-disjoint sum-bit duplicated adder.
Proceedings of the 9th European Test Symposium, 2004

A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.
Proceedings of the 2004 Design, 2004

Self-checking Carry-selectAdder with Sum-bit Duplication.
Proceedings of the ARCS 2004, 2004

2003
Multimode scan: Test per clock BIST for IP cores.
ACM Trans. Design Autom. Electr. Syst., 2003

A Modulo p Checked Self-Checking Carry Select Adder.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

2002
Scan-Path with Directly Duplicated and Inverted Duplicated Registers.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A New Self-Checking Code-Disjoint Carry-Skip Adder.
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

Partially Duplicated Code-Disjoint Carry-Skip Adder.
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001
Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging.
Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Code-Disjoint Carry-Dependent Sum Adder with Partial Look-Ahead.
Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1999
A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing.
J. Electron. Test., 1999

A New Totally Error Propagating Compactor for Arbitrary Cores with Digital Interfaces.
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999

Testability evaluation of sequential designs incorporating the multi-mode scannable memory element.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
A Structural Approach for Space Compaction for Concurrent Checking and BIST.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1997
A linear code-preserving signature analyzer COPMISR.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Code-Disjoint Circuits for Parity Circuits.
Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996
Self-Checking Comparator with One Periodic Output.
IEEE Trans. Computers, 1996

A parity-preserving multi-input signature analyzer and its application for concurrent checking and BIST.
J. Electron. Test., 1996

Concurrently self-testing embedded checkers for ultra-reliable fault-tolerant systems.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

1994
Code disjoint self-parity combinational circuits for self-testing, concurrent fault detection and parity scan design.
Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

1993
Design of self-testing and on-line fault detection combinational circuits with weakly independent outputs.
J. Electron. Test., 1993

Self-parity cominational circuits for self-testing, concurrent fault detection and parity scan design.
Proceedings of the VLSI 93, 1993

Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992
Self-testing and self-checking combinational circuits with weakly independent outputs.
Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992


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