Fernando Gehm Moraes

According to our database1, Fernando Gehm Moraes authored at least 197 papers between 1994 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2020
Surfing on curved surfaces - The Maple Package Surf.
Comput. Phys. Commun., 2020

2019
Self-Adaptive QoS Management of Computation and Communication Resources in Many-Core SoCs.
ACM Trans. Embedded Comput. Syst., 2019

Hierarchical adaptive Multi-objective resource management for many-core systems.
J. Syst. Archit., 2019

The power impact of hardware and software actuators on self-adaptable many-core systems.
J. Syst. Archit., 2019

Memphis: a framework for heterogeneous many-core SoCs generation and validation.
Design Autom. for Emb. Sys., 2019

Fine-grain temperature monitoring for many-core systems.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Lightweight security mechanisms for MPSoCs.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

An IR-UWB pulse generator using PAM modulation with adaptive PSD in 130nm CMOS process.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

A FPGA parameterizable multi-layer architecture for CNNs.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Distributed SDN architecture for NoC-based many-core SoCs.
Proceedings of the 13th IEEE/ACM International Symposium on Networks-on-Chip, 2019

A Framework for Heterogeneous Many-core SoCs Generation.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

Security in Many-Core SoCs Leveraged by Opaque Secure Zones.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

2018
A Hierarchical and Distributed Fault Tolerant Proposal for NoC-Based MPSoCs.
IEEE Trans. Emerging Topics Comput., 2018

Exploring Asynchronous End-to-End Communication Through a Synchronous NoC.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Secure Environment Architecture for MPSoCs.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Fault-Tolerance at the Management Level in Many-Core Systems.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Evaluating the cost to cipher the NoC communication.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Runtime creation of continuous secure zones in many-core systems for secure applications.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Software-Defined Networking Architecture for NoC-based Many-Cores.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An LSSD Compliant Scan Cell for Flip-Flops.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Exploring RSA Performance up to 4096-bit for Fast Security Processing on a Flexible Instruction Set Architecture Processor.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Evaluating Serialization for a Publish-Subscribe Based Middleware for MPSoCs.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Secure Admission of Applications in Many-cores.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
BrNoC: A broadcast NoC for control messages in many-core systems.
Microelectron. J., 2017

Distributed Runtime Energy Management for Many-Core Systems Running Real-Time Applications.
J. Low Power Electronics, 2017

Exploiting performance, dynamic power and energy scaling in full-system simulators.
Concurrency and Computation: Practice and Experience, 2017

System management recovery protocol for MPSoCs.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Secure admission and execution of applications in many-core systems.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Estimation methods for static noise margins in CMOS subthreshold logic circuits.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Hardware and software infrastructure to implement many-core systems in modern FPGAs.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

SDN-Based Circuit-Switching for Many-Cores.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Demystifying the cost of task migration in distributed memory many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Runtime energy management under real-time constraints in MPSoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Activation of secure zones in many-core systems with dynamic rerouting.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

XGT4: An industrial grade, open source tester for multi-gigabit networks.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017

2016
Hierarchical energy monitoring for task mapping in many-core systems.
J. Syst. Archit., 2016

MPSoCBench: A benchmark for high-level evaluation of multiprocessor system-on-chip tools and methodologies.
J. Parallel Distributed Comput., 2016

A lightweight software-based runtime temperature monitoring model for multiprocessor embedded systems.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A layered approach for fault tolerant NoC-based MPSoCs - Special session: Dependable MPSoCs.
Proceedings of the 17th Latin-American Test Symposium, 2016

DMNI: A specialized network interface for NoC-based MPSoCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Efficient traffic balancing for NoC routing latency minimization.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A data extraction and debugging framework for large-scale MPSoCs.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Runtime energy management for many-core systems.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Mapping of real-time applications on a packet switching NoC-based MPSoC.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Scalability evaluation in many-core systems due to the memory organization.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor systems.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Dynamic Real-Time Scheduler for Large-Scale MPSoCs.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
Runtime Adaptive Circuit Switching and Flow Priority in NoC-Based MPSoCs.
IEEE Trans. VLSI Syst., 2015

Static Differential NCL Gates: Toward Low Power.
IEEE Trans. on Circuits and Systems, 2015

A Distributed Energy-aware Task Mapping to Achieve Thermal Balancing and Improve Reliability of Many-core Systems.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

SDDS-NCL Design: Analysis of Supply Voltage Scaling.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A digitally controlled oscillator for fine-grained local clock generators in MPSoCs.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

BAT-Hermes: A transition-signaling bundled-data NoC router.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Trading-off system load and communication in mapping heuristics for improving NoC-based MPSoCs reliability.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A context saving fault tolerant approach for a shared memory many-core architecture.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

An integrated method for implementing online fault detection in NoC-based MPSoCs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Fault recovery protocol for distributed memory MPSoCs.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Differentiation of MPSoCs message classes using multiple NoCs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A hierarchical LST-based task scheduler for NoC-based MPSoCs with slack-time monitoring support.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Hierarchical energy monitoring for many-core systems.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A platform-based design framework to boost many-core software development.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

A non-intrusive and reconfigurable access control to secure NoCs.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014
Beware the Dynamic C-Element.
IEEE Trans. VLSI Syst., 2014

Differentiated Communication Services for NoC-Based MPSoCs.
IEEE Trans. Computers, 2014

MoNoC: A monitored network on chip with path adaptation mechanism.
J. Syst. Archit., 2014

Spatially Distributed Dual-Spacer Null Convention Logic Design.
J. Low Power Electronics, 2014

A Fast Runtime Fault Recovery Approach for NoC-Based MPSoCS for Performance Constrained Applications.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Runtime QoS Support for MPSoC: a Processor Centric Approach.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Fast energy evaluation of embedded applications for many-core systems.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

Runtime fault recovery protocol for NoC-based MPSoCs.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A framework for MPSoC generation and distributed applications evaluation.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Tool-set for NoC-based MPSoC debugging - A protocol view perspective.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A monitored NoC with runtime path adaptation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Effects of the NoC architecture in the performance of NoC-based MPSoCs.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

A method for NoC-based MPSoC energy consumption estimation.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach.
ACM Trans. Embedded Comput. Syst., 2013

Fault recovery communication protocol for NoC-based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Distributed resource management in NoC-based MPSoCs with dynamic cluster sizes.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Determining the test sources/sinks for NoC TAMs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Adaptive QoS techniques for NoC-based MPSoCs.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Achieving QoS in NoC-based MPSoCs through Dynamic Frequency Scaling.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Evaluating the scalability of test buses.
Proceedings of the 2013 International Symposium on System on Chip, 2013

Multi-level MPSoC modeling for reducing software development cycle.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Charge sharing aware NCL gates design.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Topology-agnostic fault-tolerant NoC routing method.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization.
TRETS, 2012

MAZENOC: Novel approach for fault-tolerant NOC routing.
Proceedings of the IEEE 25th International SOC Conference, 2012

Power consumption reduction in MPSoCs through DFS.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

A spectrum of MPSoC models for design space exploration and its use.
Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Comparative analysis of dynamic task mapping heuristics in heterogeneous NoC-based MPSoCs.
Proceedings of the 2012 International Symposium on System on Chip, 2012

Impact of C-elements in asynchronous circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Proposal and evaluation of a task migration protocol for NoC-based MPSoCs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A generic FPGA emulation framework.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Evaluation of adaptive management techniques in NoC-Based MPSoCs.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Enhancing performance of MPSoCs through distributed resource management.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

2011
CAFES: A framework for intrachip application modeling and communication architecture design.
J. Parallel Distributed Comput., 2011

A new test scheduling algorithm based on Networks-on-Chip as Test Access Mechanisms.
J. Parallel Distributed Comput., 2011

A Robust Architectural Approach for Cryptographic Algorithms Using GALS Pipelines.
IEEE Design & Test of Computers, 2011

Exploring NoC-Based MPSoC Design Space with Power Estimation Models.
IEEE Design & Test of Computers, 2011

A self-adaptable distributed DFS scheme for NoC-based MPSoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Multi-task dynamic mapping onto NoC-based MPSoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Energy-efficient cache coherence protocol for NoC-based MPSoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Early estimation of wire length for dedicated test access mechanisms in networks-on-chip based SoCs.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

Arbitration and routing impact on NoC design.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.
Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

HeMPS-S: A homogeneous NoC-based MPSoCs framework prototyped in FPGAs.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Exploring heterogeneous NoC-based MPSoCs: From FPGA to high-level modeling.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Exploiting multicast messages in cache-coherence protocols for NoC-based MPSoCs.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Energy-aware dynamic task mapping for NoC-based MPSoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Predictive Dynamic Frequency Scaling for Multi-Processor Systems-on-Chip.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Adapting a C-element design flow for low power.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Dynamic Flow Reconfiguration Strategy to Avoid Communication Hot-Spots.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Achieving composability in NoC-based MPSoCs through QoS management at software level.
Proceedings of the Design, Automation and Test in Europe, 2011

Evaluating energy consumption of homogeneous MPSoCs using spare tiles.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Joint Validation of Application Models and Multi-Abstraction Network-on-Chip Platforms.
IJERTCS, 2010

Dynamic Task Mapping for MPSoCs.
IEEE Design & Test of Computers, 2010

Hermes-AA: A 65nm asynchronous NoC router with adaptive routing.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Flow oriented routing for NOCS.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Evaluating the impact of task migration in multi-processor systems-on-chip.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

Hermes-A - An Asynchronous NoC Router with Distributed Routing.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010

Model-based design flow for NoC-based MPSoCs.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Improving QoS of Multi-layer Networks-on-Chip with Partial and Dynamic Reconfiguration of Routers.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

2009
Crosstalk Fault Tolerant NoC: Design and Evaluation.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009

A path-load based adaptive routing algorithm for networks-on-chip.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

A high abstraction, high accuracy power estimation model for networks-on-chip.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Floating Point Hardware for Embedded Processors in FPGAs: Design Space Exploration for Performance and Area.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

A 10 Gbps OTN Framer Implementation Targeting FPGA Devices.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Increasing NoC power estimation accuracy through a rate-based model.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

HeMPS - a Framework for NoC-based MPSoC Generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
Comparison of network-on-chip mapping algorithms targeting low energy consumption.
IET Computers & Digital Techniques, 2008

Validation of executable application models mapped onto network-on-chip platforms.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

A simplified executable model to evaluate latency and throughput of networks-on-chip.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

MOTIM: an industrial application using nocs.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

Applying UML Interactions and Actor-Oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

NoC Power Estimation at the RTL Abstraction Level.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Deadlock-Free Multicast Routing Algorithm for Wormhole-Switched Mesh Networks-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

2007
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
IET Computers & Digital Techniques, 2007

DfT for the Reuse of Networks-on-Chip as Test Access Mechanism.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

QoS in Networks-on-Chip - Beyond Priority and Circuit Switching Techniques.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007

Buffer sizing for QoS flows in wormhole packet switching NoCs.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Router architecture for high-performance NoCs.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Architectural Issues in Homogeneous NoC-Based MPSoC.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Heuristics for Dynamic Task Mapping in NoC-based Heterogeneous MPSoCs.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

SPP-NIDS - A Sea of Processors Platform for Network Intrusion Detection Systems.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Communication Models in Networks-on-Chip.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

Inserting Data Encoding Techniques into NoC-Based Systems.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Congestion-Aware Task Mapping in NoC-based MPSoCs with Dynamic Workload.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

MOTIM - A Scalable Architecture for Ethernet Switches.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Evaluation of Algorithms for Low Energy Mapping onto NoCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

Reducing the Power Consumption in Networks-on-Chip through Data Coding Schemes.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

SCAFFI: An intrachip FPGA asynchronous interface based on hard macros.
Proceedings of the 25th International Conference on Computer Design, 2007

Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.
Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006
Application driven traffic modeling for NoCs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Infrastructure for dynamic reconfigurable systems: choices and trade-offs.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006

Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Reconfigurable Systems Enabled by a Network-on-Chip.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Leak Resistant Architecture Against Side Channel Attacks.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
Proceedings of the 11th European Test Symposium, 2006

2005
Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Traffic generation and performance evaluation for mesh-based NoCs.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Current mask generation: a transistor level security against DPA attacks.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Virtual channels in networks on chip: implementation and evaluation on hermes NoC.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

A new hardware countermeasure for masking power signatures of crypto cores.
Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

A scalable test strategy for network-on-chip routers.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.
Proceedings of the 2005 Design, 2005

Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture.
Proceedings of the 2005 Design, 2005

MAIA: a framework for networks on chip generation and verification.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
HERMES: an infrastructure for low area overhead packet-switching networks on chip.
Integr., 2004

PaDReH: a framework for the design and implementation of dynamically and partially reconfigurable systems.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Reducing test time with processor reuse in network-on-chip based systems.
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications.
Proceedings of the Field Programmable Logic and Application, 2004

MultiNoC: A Multiprocessing System Enabled by a Network on Chip.
Proceedings of the 2004 Design, 2004

2003
A Low Area Overhead Packet-switched Network on Chip: Architecture and Prototyping.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Are coarse grain reconfigurable architectures suitable for cryptography?
Proceedings of the IFIP VLSI-SoC 2003, 2003

Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Software-Based Test for Non-Programmable Cores in Bus-Based System-on-Chip Architectures.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003

Exploiting reconfigurability for low-power control of embedded processors.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Remote and Partial Reconfiguration of FPGAs: Tools and Trends.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Propose of a Hardware Implementation for Fingerprint Systems.
Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Design of a fingerprint system using a hardware/software environment.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

Development of a Tool-Set for Remote and Partial Reconfiguration of FPGAs.
Proceedings of the 2003 Design, 2003

2002
Prototyping of embedded digital systems from SDL language: a case study.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

2001
Integrating the teaching of computer organization and architecture with digital hardware design early in undergraduate courses.
IEEE Trans. Education, 2001

Projeto para Prototipação de um IP Soft Core MAC Ethernet.
RITA, 2001

1999
A Virtual CMOS Library Approach for East Layout Synthesis.
Proceedings of the VLSI: Systems on a Chip, 1999

1994
Influence of Locig Block Layout Architecture on FPGA Performance.
Proceedings of the Field-Programmable Logic, 1994


  Loading...