Felipe T. Bortolon

Orcid: 0000-0001-6288-978X

According to our database1, Felipe T. Bortolon authored at least 7 papers between 2013 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2021
Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator.
IET Comput. Digit. Tech., 2021

2018
Evaluation of Compiler Optimization Flags Effects on Soft Error Resiliency.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Exploring the Impact of Soft Errors on NoC-based Multiprocessor Systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Estimation methods for static noise margins in CMOS subthreshold logic circuits.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Hardware and software infrastructure to implement many-core systems in modern FPGAs.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

2016
Design and analysis of the HF-RISC processor targeting voltage scaling applications.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

2013
An implementation of a distributed fault-tolerant mechanism for 2D mesh NoCs.
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013


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