Vivekananda M. Vedula

According to our database, Vivekananda M. Vedula authored at least 14 papers between 2000 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2011

A Unified Formal Framework for Analyzing Functional and Speed-path Properties.

Oswaldo Olivo, Sandip Ray, Jayanta Bhadra, Vivekananda M. Vedula

Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

2008

Automatic Constraint Based Test Generation for Behavioral HDL Models.

Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti, Vivekananda M. Vedula, K. S. Maneperambil

IEEE Trans. Very Large Scale Integr. Syst., 2008

2007

Controllability-Driven Peak Dynamic Power Estimation for VLSI Circuits.

K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula

J. Low Power Electron., 2007

Power Virus Generation Using Behavioral Models of Circuits.

K. Najeeb, Vishnu Vardhan Reddy Konda, Siva Kumar Sastry Hari, V. Kamakoti, Vivekananda M. Vedula

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Controllability-driven Power Virus Generation for Digital Circuits.

K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Scalable Symbolic Simulator for Verilog RTL.

Sasidhar Sunkari, Supratik Chakraborty, Vivekananda M. Vedula, Kailasnath Maneparambil

Proceedings of the Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), 2007

2004

Program Slicing for ATPG-Based Property Checking.

Vivekananda M. Vedula, Whitney J. Townsend, Jacob A. Abraham

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.

Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra, Raghuram S. Tupuri

J. Electron. Test., 2003

Formal Verification Using Bounded Model Checking: SAT versus Sequential ATPG Engines.

Daniel G. Saab, Jacob A. Abraham, Vivekananda M. Vedula

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

2002

Program Slicing for Hierarchical Test Generation.

Vivekananda M. Vedula, Jacob A. Abraham, Jayanta Bhadra

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Verifying Properties Using Sequential ATPG.

Jacob A. Abraham, Vivekananda M. Vedula, Daniel G. Saab

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Native Mode Functional Self-Test Generation for Systems-on-Chip.

Kamalnayan Jayaraman, Vivekananda M. Vedula, Jacob A. Abraham

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis.

Vivekananda M. Vedula, Jacob A. Abraham

Proceedings of the 2002 Design, 2002

2000

A novel methodology for hierarchical test generation using functional constraint composition.

Vivekananda M. Vedula, Jacob A. Abraham

Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000