Vladimir Afonso

Orcid: 0000-0002-5761-4121

According to our database1, Vladimir Afonso authored at least 23 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
An UHD 4K@120fps Hardware for the VVC Prediction Refinement with Optical Flow.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

2022
Quality-power configurable flexible coding order hardware design for real-time 3D-HEVC intra-frame prediction.
J. Real Time Image Process., 2022

2021
Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing.
J. Real Time Image Process., 2021

2020
6WR: A Hardware Friendly 3D-HEVC DMM-1 Algorithm and its Energy-Aware and High-Throughput Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Complexity and compression efficiency assessment of 3D-HEVC encoder.
Multim. Tools Appl., 2020

High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction.
IEEE Des. Test, 2020

High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
IEEE Des. Test, 2020

A Hardware Design for 3D-HEVC Depth Intra Skip with Synthesized View Distortion Change.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

A Low-Complexity Algorithm and Its Low-Power and High-Throughput Architecture for 3D-HEVC DMM-1 Encoding Tool.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

2019
Energy-Aware Motion and Disparity Estimation System for 3D-HEVC With Run-Time Adaptive Memory Hierarchy.
IEEE Trans. Circuits Syst. Video Technol., 2019

2018
Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

ASIC power-estimation accuracy evaluation: A case study using video-coding architectures.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
An efficient sub-sample interpolator hardware for VP9-10 standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A multi-standard interpolation filter for motion compensated prediction on high definition videos.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A multi-standard interpolation hardware solution for H.264 and HEVC.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

2014
HEVC Fractional Motion Estimation complexity reduction for real-time applications.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

2013
Low cost and high throughput FME interpolation for the HEVC emerging video coding standard.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Simplified HEVC FME Interpolation Unit Targeting a Low Cost and High Throughput Hardware Design.
Proceedings of the 2013 Data Compression Conference, 2013


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