Wagner Penny

Orcid: 0000-0003-2227-1218

According to our database1, Wagner Penny authored at least 18 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
High-Throughput and Multiplierless Hardware Design for the AV1 Fractional Motion Estimation.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation.
Proceedings of the IEEE International Conference on Image Processing, 2023

2022
Hardware Design for the Separable Symmetric Normalized Wiener Filter of the AV1 Decoder.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

2020
Power/QoS-Adaptive HEVC FME Hardware using Machine Learning-Based Approximation Control.
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020

Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019
High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator.
J. Real Time Image Process., 2019

Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Design Space Exploration of HEVC RCL Mapped onto NoC-Based Embedded Platforms.
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Configurable Cache Memory Architecture for Low-Energy Motion Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
Cache Memory Energy Efficiency Exploration for the HEVC Motion Estimation.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

Characterizing energy consumption in software HEVC encoders: HM vs x265.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

2016
Pareto-based energy control for the HEVC encoder.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

An efficient sub-sample interpolator hardware for VP9-10 standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

2015
Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015


  Loading...