Bruno Zatt

Orcid: 0000-0002-8045-957X

According to our database1, Bruno Zatt authored at least 207 papers between 2006 and 2024.

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Bibliography

2024
A systematic literature review on video transcoding acceleration: challenges, solutions, and trends.
Multim. Tools Appl., July, 2024

Memory-Centered Motion Estimation System With CTB-Based Full-Splitting Algorithm.
IEEE Trans. Consumer Electron., May, 2024

Multi-Codec Video Quality Enhancement Model Based on Spatio- Temporal Deformable Fusion.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Neural Network Based Light Field Predictors: An Evaluation.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Improving Video Streaming Quality in Congested Networks with In-Network Computing.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

Error-Resilience Profiling of Inter-Frame Prediction at VVC Encoders for Approximate Storage.
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024

2023
SBCCI 2022.
IEEE Des. Test, October, 2023

Complexity and compression efficiency analysis of libaom AV1 video codec.
J. Real Time Image Process., June, 2023

A High-Throughput Hardware Design for the AV1 Decoder Intraprediction.
IEEE Trans. Very Large Scale Integr. Syst., April, 2023

A Machine Learning-Based Solution to Accelerate the Intra Mode Decision for the VVC Standard.
Proceedings of the 29th Brazilian Symposium on Multimedia and the Web, 2023

Using Decision Trees to Accelerate the H.266/VVC-to-AV1 Video Transcoding.
Proceedings of the 36th SIBGRAPI Conference on Graphics, Patterns and Images, 2023

Evaluation of Imprecise Subtractors into Test Zone Search for VVC Encoding.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Error Resilience Evaluation of Approximate Storage in the Motion Compensation of VVC Decoders.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

High-Throughput and Multiplierless Hardware Design for the AV1 Fractional Motion Estimation.
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023

High-Throughput Design for a Multi-Size DCT-II Targeting the AV1 Encoder.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Fast Intra Mode Decision Using Machine Learning for the Versatile Video Coding Standard.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

H.264-to-AV1 Video Transcoding Acceleration Based on Lightweight Machine Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

High-Throughput and Multiplierless Hardware Design for the AV1 Local Warped MC Interpolation.
Proceedings of the IEEE International Conference on Image Processing, 2023

2022
FastInter360: A Fast Inter Mode Decision for HEVC 360 Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2022

Quality-power configurable flexible coding order hardware design for real-time 3D-HEVC intra-frame prediction.
J. Real Time Image Process., 2022

Guest Editors' Introduction: SBCCI 2021.
IEEE Des. Test, 2022

Novel Light Field Encoding Framework Based on Optical Flow and Phase Correlation.
Proceedings of the WebMedia '22: Brazilian Symposium on Multimedia and Web, Curitiba, Brazil, November 7, 2022

A Learning-Based Framework for Depth Perception using Dense Light Fields.
Proceedings of the WebMedia '22: Brazilian Symposium on Multimedia and Web, Curitiba, Brazil, November 7, 2022

Full Reference Stereoscopic Objective Quality Assessment using Lightweight Machine Learning.
Proceedings of the WebMedia '22: Brazilian Symposium on Multimedia and Web, Curitiba, Brazil, November 7, 2022

Error Resilience Evaluation of Approximate Storage in the Intra Prediction of VVC Decoders.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Low-Frequency Non-Separable Transform Hardware System Design for the VVC Encoder.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022

Video Decoder Improvements with Near-Data Speculative Motion Compensation Processing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A High-Throughput Design for the H.266/VVC Low-Frequency Non-Separable Transform.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Improving Content-Aware Video Streaming in Congested Networks with In-Network Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Fast Affine Motion Estimation for VVC using Machine-Learning-Based Early Search Termination.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Low-Complexity Multi-Type Tree Partitioning for Versatile Video Coding Based on Machine Learning.
Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

VVC Interpicture Prediction Using SAD with Imprecise Subtractors: A Quantitative Analysis.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

2021
Energy-Throughput Configurable Design for Video Processing Binary Arithmetic Encoder.
IEEE Trans. Circuits Syst. Video Technol., 2021

AV1 and VVC Video Codecs: Overview on Complexity Reduction and Hardware Design.
IEEE Open J. Circuits Syst., 2021

Low-energy motion estimation memory system with dynamic management.
J. Real Time Image Process., 2021

Fast and energy-efficient approximate motion estimation architecture for real-time 4 K UHD processing.
J. Real Time Image Process., 2021

Coding mode decision algorithm for fast HEVC transrating using heuristics and machine learning.
J. Real Time Image Process., 2021

Complexity-scalable HEVC-to-AV1 video transcoding based on partition inheritance.
J. Real Time Image Process., 2021

A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Low-Power and High-Throughput Approximated Architecture for AV1 FME Interpolation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Residual Syntax Elements Analysis and Design Targeting High-Throughput HEVC CABAC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Complexity and compression efficiency assessment of 3D-HEVC encoder.
Multim. Tools Appl., 2020

Speedup evaluation of HEVC parallel video coding using Tiles.
J. Real Time Image Process., 2020

UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders.
J. Real Time Image Process., 2020

High-Throughput Hardware for 3D-HEVC Depth-Map Intra Prediction.
IEEE Des. Test, 2020

High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
IEEE Des. Test, 2020

Power/QoS-Adaptive HEVC FME Hardware using Machine Learning-Based Approximation Control.
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020

4D-DCT Hardware Architecture for JPEG Pleno Light Field Coding.
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020

ERP-Based CTU Splitting Early Termination for Intra Prediction of 360 videos.
Proceedings of the 2020 IEEE International Conference on Visual Communications and Image Processing, 2020

Evaluation of Cache-Based Memory Hierarchy for HEVC Video Decoding.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

2PSA: An Optimized and Flexible Power-Precision Scalable Adder.
Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

A Reliability-Oriented Machine Learning Strategy for Heterogeneous Multicore Application Mapping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Low-Power and Memory-Aware Approximate Hardware Architecture for Fractional Motion Estimation Interpolation on HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Memory Assessment Of Versatile Video Coding.
Proceedings of the IEEE International Conference on Image Processing, 2020

An Overview of Dedicated Hardware Designs for State-of-the-Art AV1 and H.266/VVC Video Codecs.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Memory Profiling of H.266 Versatile Video Coding Standard.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Spatially Adaptive Intra Mode Pre-Selection for ERP 360 Video Coding.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

RDE-MOGA: Automatic Selection of Rate-Distortion-Energy Control Points for Video Encoders Using Muti-Objetive Genetic Algorithm.
Proceedings of the 2020 IEEE International Conference on Acoustics, 2020

ESA360 - Early SKIP Mode Decision Algorithm for Fast ERP 360 Video Coding.
Proceedings of the 28th European Signal Processing Conference, 2020

Low-Complexity HEVC Transrating Based on Prediction Unit Mode Inheritance.
Proceedings of the 28th European Signal Processing Conference, 2020

Fast VP9-to-AV1 Transcoding based on Block Partitioning Inheritance.
Proceedings of the 28th European Signal Processing Conference, 2020

Diagnosis of Apple Fruit Diseases in the Wild with Mask R-CNN.
Proceedings of the Intelligent Systems - 9th Brazilian Conference, 2020

2019
Hybrid Scratchpad Video Memory Architecture for Energy-Efficient Parallel HEVC.
IEEE Trans. Circuits Syst. Video Technol., 2019

Fast Coding Unit Partition Decision for HEVC Using Support Vector Machines.
IEEE Trans. Circuits Syst. Video Technol., 2019

Energy-Aware Motion and Disparity Estimation System for 3D-HEVC With Run-Time Adaptive Memory Hierarchy.
IEEE Trans. Circuits Syst. Video Technol., 2019

High-Throughput Multifilter Interpolation Architecture for AV1 Motion Compensation.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Quality and Energy-Aware HEVC Transrating Based on Machine Learning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Efficient reference frame compression scheme for video coding systems: algorithm and VLSI design.
J. Real Time Image Process., 2019

High-throughput and power-efficient hardware design for a multiple video coding standard sample interpolator.
J. Real Time Image Process., 2019

Energy-aware cache hierarchy assessment targeting HEVC encoder execution.
J. Real Time Image Process., 2019

Evaluation of machine learning algorithms for fast video transcoding in streaming services.
Proceedings of the 25th Brazillian Symposium on Multimedia and the Web, 2019

Performance evaluation of HEVC RCL applications mapped onto NoC-based embedded platforms.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Hardware design of DC/CFL intra-prediction decoder for the AV1 codec.
Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design, 2019

Design Space Exploration of HEVC RCL Mapped onto NoC-Based Embedded Platforms.
Proceedings of the 14th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2019

Power-Efficient Approximate SAD Architecture with LOA Imprecise Adders.
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

TITAN: Tile Timing-Aware Balancing Algorithm for Speeding Up the 3D-HEVC Intra Coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

High Throughput Hardware Design for AV1 Paeth and Smooth Intra Modes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Fast Hevc-to-Av1 Transcoding Based On Coding Unit Depth Inheritance.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

Energy-Efficiency Exploration of Memory Hierarchy using NVMs for HEVC Motion Estimation.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Approximate Subtractor Operator for Low-Power Video Coding Hardware Accelerators.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

A New Hardware Friendly 2D-DCT HEVC Compliant Algorithm and its High Throughput and Low Power Hardware Design.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Coding Tree Early Termination for Fast HEVC Transrating Based on Random Forests.
Proceedings of the IEEE International Conference on Acoustics, 2019

A Fast Local Mode Decision for the HEVC Intra Prediction Based on Direction Detection.
Proceedings of the 27th European Signal Processing Conference, 2019

Complexity Scalable HEVC-to-AV1 Transcoding Based on Coding Tree Depth Inheritance.
Proceedings of the 27th European Signal Processing Conference, 2019

FastIntra360: A Fast Intra-Prediction Technique for 360-Degrees Video Coding.
Proceedings of the Data Compression Conference, 2019

2018
Reference frame context-adaptive variable-length coder: a real-time hardware-friendly approach for lossless external memory bandwidth reduction in current video-coding systems.
J. Real Time Image Process., 2018

Exploring Heterogeneous Task-Level Parallelism in a BMA Video Coding Application using System-Level Simulation.
Proceedings of the VIII Brazilian Symposium on Computing Systems Engineering, 2018

Low-Power and High-Throughput Architecture for 3D-HEVC Depth Modeling Mode 4.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A Power-Efficient and High-Throughput Hardware Design for 3D-HEVC Disparity Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

High Throughput Multiplierless Architecture for VP9 Fractional Motion Estimation.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Low-Power HEVC 1-D IDCT Hardware Architecture.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Hybrid Memory Cube in Embedded Systems.
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

ASIC power-estimation accuracy evaluation: A case study using video-coding architectures.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

Fast and energy-efficient HEVC transrating based on frame partitioning inheritance.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

High-Throughput Binary Arithmetic Encoder using Multiple-Bypass Bins Processing for HEVC CABAC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Configurable Cache Memory Architecture for Low-Energy Motion Estimation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

OTED: Encoding Optimization Technique Targeting Energy-Efficient HEVC Decoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High-Throughput and Low-Power Integrated Direct/Inverse HEVC Quantization Hardware Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Hardware-Friendly Unidirectional Disparity-Search Algorithm for 3D-HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

LF-CAE: Context-Adaptive Encoding for Lenslet Light Fields Using HEVC.
Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Memory-Aware Tiles Workload Balance through Machine-Learnt Complexity Reduction for HEVC.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

HEVC Residual Syntax Elements Generation Architecture for High-Throughput CABAC Design.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Power-Efficient and Memory-Aware Approximate Hardware Design for HEVC FME Interpolator.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Learning-Based Complexity Reduction and Scaling for HEVC Encoders.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Octagonal-Axis Raster Pattern for Improved Test Zone Search Motion Estimation.
Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017
Application-Guided Power-Efficient Fault Tolerance for H.264 Context Adaptive Variable Length Coding.
IEEE Trans. Computers, 2017

Energy-aware scheme for the 3D-HEVC depth maps prediction.
J. Real Time Image Process., 2017

Complexity control of HEVC encoders targeting real-time constraints.
J. Real Time Image Process., 2017

Rate and Complexity-Aware Coding Scheme for Fixed-Camera Videos Based on Region-of-Interest Detection.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Objective and Subjective Video Quality Assessment in Mobile Devices for Low-Complexity H.264/AVC Codecs.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Video Quality Assessment of Early SKIP/DIS for 3D-HEVC Complexity Reduction.
Proceedings of the 23rd Brazillian Symposium on Multimedia and the Web, 2017

Cache Memory Energy Efficiency Exploration for the HEVC Motion Estimation.
Proceedings of the VII Brazilian Symposium on Computing Systems Engineering, 2017

Novel multiple bypass bins scheme for low-power UHD video processing HEVC binary arithmetic encoder architecture.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Segmented spline hardware design for high dynamic range video pre-processor.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low-power multi-size HEVC DCT architecture proposal for QFHD video processing.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low-power HEVC binarizer architecture for the CABAC block targeting UHD video processing.
Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Energy-efficient motion estimation with approximate arithmetic.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017

Multiple early-termination scheme for TZ search algorithm based on data mining and decision trees.
Proceedings of the 19th IEEE International Workshop on Multimedia Signal Processing, 2017

Characterizing energy consumption in software HEVC encoders: HM vs x265.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Energy evaluation of the HEVC decoding for different encoding configurations.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

High-throughput HEVC intrapicture prediction hardware design targeting UHD 8K videos.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A multiplierless parallel HEVC quantization hardware for real-time UHD 8K video coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Edge-aware depth motion estimation - A complexity reduction scheme for 3D-HEVC.
Proceedings of the 25th European Signal Processing Conference, 2017

Complexity reduction of 3D-HEVC based on depth analysis for background and ROI classification.
Proceedings of the 25th European Signal Processing Conference, 2017

2016
Low-power hardware design for the HEVC Binary Arithmetic Encoder targeting 8K videos.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A parallel Motion Estimation solution for heterogeneous System on Chip.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Complexity-scalable HEVC encoding.
Proceedings of the 2016 Picture Coding Symposium, 2016

Solutions for DMM-1 complexity reduction in 3D-HEVC based on gradient calculation.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy analisys of motion estimation memory transference on embedded processors.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Rate-distortion-complexity analysis for prediction unit modes in 3D-HEVC depth coding.
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016

Energy-aware cache assessment of HEVC decoding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An HEVC multi-size DCT hardware with constant throughput and supporting heterogeneous CUs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Speedup-aware history-based tiling algorithm for the HEVC standard.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Pareto-based energy control for the HEVC encoder.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

An efficient sub-sample interpolator hardware for VP9-10 standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

High-throughput and memory-aware hardware of a sub-pixel interpolator for multiple video coding standards.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Complexity reduction for 3D-HEVC depth map coding based on early Skip and early DIS scheme.
Proceedings of the 2016 IEEE International Conference on Image Processing, 2016

Real-time simplified edge detector architecture for 3D-HEVC depth maps coding.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
DMMFast: a complexity reduction scheme for three-dimensional high-efficiency video coding intraframe depth map coding.
J. Electronic Imaging, 2015

Real-Time Architecture for HEVC Motion Compensation Sample Interpolator for UHD Videos.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

A Low-Area and High-Throughput Intra Prediction Architecture for a Multi-Standard HEVC and H.264/AVC Video Encoder.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Memory-Aware and High-Throughput Hardware Design for the HEVC Fractional Motion Estimation.
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

S-GMOF: A gradient-based complexity reduction algorithm for depth-maps intra prediction on 3D-HEVC.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A multi-standard interpolation filter for motion compensated prediction on high definition videos.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Hardware design of fast HEVC 2-D IDCT targeting real-time UHD 4K applications.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A real-time architecture for reference frame compression for high definition video coders.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Complexity reduction for the 3D-HEVC depth maps coding.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Rate-distortion and energy performance of HEVC and H.264/AVC encoders: A comparative analysis.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A multi-standard interpolation hardware solution for H.264 and HEVC.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015

Approximation-aware Multi-Level Cells STT-RAM cache architecture.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
Parallelization of Full Search Motion Estimation Algorithm for Parallel and Distributed Platforms.
Int. J. Parallel Program., 2014

A complexity reduction algorithm for depth maps intra prediction on the 3D-HEVC.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

Sample adaptive offset filter hardware design for HEVC encoder.
Proceedings of the 2014 IEEE Visual Communications and Image Processing Conference, 2014

A Real-Time 5-Views HD 1080p Architecture for 3D-HEVC Depth Modeling Mode 4.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

A Memory Energy Consumption Analysis of Motion Estimation Algorithms using Data Reuse in Video Coding Systems.
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014

Rate-distortion and energy performance of HEVC video encoders.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014

An efficient reference frame compression approach for video coding systems.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

HEVC Fractional Motion Estimation complexity reduction for real-time applications.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Configurable hardware design for the HEVC-based Adaptive Loop Filter.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Overview and quality analysis in 3D-HEVC emergent video coding standard.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Memory energy consumption reduction in video coding systems.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Content-driven memory pressure balancing and video memory power management for parallel high efficiency video coding.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Memory bandwidth reduction for H.264 and HEVC encoders using lossless reference frame coding.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Power efficient and high troughtput multi-size IDCT targeting UHD HEVC decoders.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A new differential and lossless Reference Frame Variable-Length Coder: An approach for high definition video coders.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Complexity reduction for 3D-HEVC depth maps intra-frame prediction using simplified edge detector algorithm.
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014

Energy-efficient architecture for advanced video memory.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A low-complexity and lossless reference frame encoder algorithm for video coding.
Proceedings of the IEEE International Conference on Acoustics, 2014

Cost function optimization and its hardware design for the Sample Adaptive Offset of HEVC standard.
Proceedings of the 22nd European Signal Processing Conference, 2014

dSVM: Energy-efficient distributed Scratchpad Video Memory Architecture for the next-generation High Efficiency Video Coding.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Model Predictive Hierarchical Rate Control With Markov Decision Process for Multiview Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2013

A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile.
J. Real Time Image Process., 2013

Adaptive content-based Tile partitioning algorithm for the HEVC standard.
Proceedings of the 30th Picture Coding Symposium, 2013

Content-adaptive reference frame compression based on intra-frame prediction for multiview video coding.
Proceedings of the IEEE International Conference on Image Processing, 2013

An energy-efficient hardware design for lossless reference frame compression in video coders.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

ES&IS: Enhanced Spread and Iterative Search hardware-friendly motion estimation algorithm for the HEVC Standard.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

High throughput hardware design for the HEVC Fractional Motion Estimation Interpolation Unit.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

Energy-efficient memory hierarchy for motion and disparity estimation in multiview video coding.
Proceedings of the Design, Automation and Test in Europe, 2013

3D Video Coding for Embedded Devices - Energy Efficient Algorithms and Architectures.
Springer, ISBN: 978-1-4614-6758-8, 2013

2012
A complexity reduction scheme with adaptive search direction and mode elimination for multiview video coding.
Proceedings of the 2012 Picture Coding Symposium, 2012

A Model Predictive Controller for Frame-Level Rate Control in Multiview Video Coding.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012

Real-time block matching motion estimation onto GPGPU.
Proceedings of the 19th IEEE International Conference on Image Processing, 2012

Power-efficient error-resiliency for H.264/AVC Context-Adaptive Variable Length Coding.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Adaptive power management of on-chip video memory for multiview video coding.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Applying CUDA Architecture to Accelerate Full Search Block Matching Algorithm for High Performance Motion Estimation in Video Encoding.
Proceedings of the 23rd International Symposium on Computer Architecture and High Performance Computing, 2011

A high throughput H.264/AVC intra-frame encoding loop architecture for HD1080p.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A multi-level dynamic complexity reduction scheme for multiview video coding.
Proceedings of the 18th IEEE International Conference on Image Processing, 2011

A low-power memory architecture with application-aware power management for motion & disparity estimation in Multiview Video Coding.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Multi-level pipelined parallel hardware architecture for high throughput motion and disparity estimation in Multiview Video Coding.
Proceedings of the Design, Automation and Test in Europe, 2011

Run-time adaptive energy-aware motion and disparity estimation in multiview video coding.
Proceedings of the 48th Design Automation Conference, 2011

2010
Timing and interface communication analysis of H.264/AVC encoder using SystemC model.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

An adaptive early skip mode decision scheme for multiview video coding.
Proceedings of the Picture Coding Symposium, 2010

Power-aware complexity-scalable multiview video coding for mobile devices.
Proceedings of the Picture Coding Symposium, 2010

Gop structure adaptive to the video content for efficient H.264/AVC encoding.
Proceedings of the International Conference on Image Processing, 2010

A high throughput CAVLC hardware architecture with parallel coefficients processing for HDTV H.264/AVC enconding.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009
A method for HW functional verification through HW/SW co-simulation in complex systems: H.264/AVC decoder as case study.
Proceedings of the 10th Latin American Test Workshop, 2009

A real time H.264/AVC intra frame prediction hardware architecture for HDTV 1080P video.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

High throughput scalable Motion Compensation architecture for H.264/SVC video coding standard.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
High throughput architecture for H.264/AVC motion compensation sample interpolator for HDTV.
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

HP422-MoCHA: A H.264/AVC High Profile motion compensation architecture for HDTV.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Design and FPGA Prototyping of a H.264/AVC Main Profile.
J. Braz. Comput. Soc., 2007

FPGA Prototyping Strategy for a H.264/AVC Video Decoder.
Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

Motion Compensation Hardware Accelerator Architecture for H.264/AVC.
Proceedings of the Advances in Image and Video Technology, Second Pacific Rim Symposium, 2007

Memory Hierarchy Targeting Bi-Predictive Motion Compensation for H.264/AVC Decoder.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
Motion Compensation Decoder Architecture for H.264/AVC Main Profile Targeting HDTV.
Proceedings of the IFIP VLSI-SoC 2006, 2006


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