Evangeline F. Y. Young

According to our database1, Evangeline F. Y. Young authored at least 159 papers between 1997 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

2021
Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Attacking a CNN-based Layout Hotspot Detector Using Group Gradient Method.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems.
ACM Trans. Design Autom. Electr. Syst., 2020

Adversarial Perturbation Attacks on ML-based CAD: A Case Study on CNN-based Lithographic Hotspot Detection.
ACM Trans. Design Autom. Electr. Syst., 2020

GAN-OPC: Mask Optimization With Lithography-Guided Generative Adversarial Nets.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Layout Pattern Generation and Legalization with Generative Learning Models.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learning.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019
Three-dimensional Floorplan Representations by Using Corner Links and Partial Order.
ACM Trans. Design Autom. Electr. Syst., 2019

Layout Hotspot Detection With Feature Tensor Generation and Deep Biased Learning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Are Adversarial Perturbations a Showstopper for ML-Based CAD? A Case Study on CNN-Based Lithographic Hotspot Detection.
CoRR, 2019

An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems.
Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019

Session details: Patterning and Machine Learning.
Proceedings of the 2019 International Symposium on Physical Design, 2019

Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction.
Proceedings of the International Conference on Computer-Aided Design, 2019

Dim Sum: Light Clock Tree by Small Diameter Sum.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Attacking Split Manufacturing from a Deep Learning Perspective.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

FIT: Fill Insertion Considering Timing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

A fast machine learning-based mask printability predictor for OPC acceleration.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Detailed routing by sparse grid graph and minimum-area-captured path search.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
CRMA: Incorporating Cut Redistribution With Mask Assignment to Enable the Fabrication of 1-D Gridded Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

STOMA: Simultaneous Template Optimization and Mask Assignment for Directed Self-Assembly Lithography With Multiple Patterning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Fast and Accurate Estimation of Quality of Results in High-Level Synthesis with Machine Learning.
Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

GAN-OPC: mask optimization with lithography-guided generative adversarial nets.
Proceedings of the 55th Annual Design Automation Conference, 2018

Routability-driven and fence-aware legalization for mixed-cell-height circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018

A two-step search engine for large scale boolean matching under NP3 equivalence.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Lithography hotspot detection: From shallow to deep learning.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

Timing driven routing tree construction.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Fence-aware detailed-routability driven placement.
Proceedings of the ACM/IEEE 2017 International Workshop on System Level Interconnect Prediction, 2017

Bilinear Lithography Hotspot Detection.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning.
Proceedings of the 54th Annual Design Automation Conference, 2017

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Slicing Floorplan Orientation.
Encyclopedia of Algorithms, 2016

Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Preface to Special Section on New Physical Design Techniques for the Next Generation of Integration Technology.
ACM Trans. Design Autom. Electr. Syst., 2016

An Effective Chemical Mechanical Polishing Fill Insertion Approach.
ACM Trans. Design Autom. Electr. Syst., 2016

Ripple 2.0: Improved Movement of Cells in Routability-Driven Placement.
ACM Trans. Design Autom. Electr. Syst., 2016

Placement: From Wirelength to Detailed Routability.
IPSJ Trans. Syst. LSI Des. Methodol., 2016

Row-structure stencil planning approaches for E-beam lithography with overlapped characters.
Integr., 2016

Enabling online learning in lithography hotspot detection with information-theoretic feature optimization.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Incorporating cut redistribution with mask assignment to enable 1D gridded design.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Optimization for Multiple Patterning Lithography with cutting process and beyond.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Legalization algorithm for multiple-row height standard cell design.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Simultaneous template optimization and mask assignment for DSA with multiple patterning.
Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

VLSI layout hotspot detection based on discriminative feature extraction.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

3D floorplan representations: Corner links and partial order.
Proceedings of the 2016 IEEE International 3D Systems Integration Conference, 2016

2015
Planning Massive Interconnects in 3-D Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

An Effective Chemical Mechanical Polishing Filling Approach.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

An effective triple patterning aware grid-based detailed routing approach.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A robust approach for process variation aware mask optimization.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Obstacle-avoiding rectilinear Steiner tree construction in sequential and parallel approach.
Integr., 2014

A Fast Hypergraph Bipartitioning Algorithm.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Cell density-driven detailed placement with displacement constraint.
Proceedings of the International Symposium on Physical Design, 2014

A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters.
Proceedings of the International Symposium on Physical Design, 2014

Reducing pin count on cross-referencing Digital Microfluidic Biochip.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Overlapping-aware throughput-driven stencil planning for E-beam lithography.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Triple patterning lithography aware optimization for standard cell based design.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only).
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

General purpose cross-referencing Microfluidic Biochip with reduced pin-count.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

Structural planning of 3D-IC interconnects by block alignment.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
ObSteiner: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees in the Presence of Complex Rectilinear Obstacles.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Ripple: A Robust and Effective Routability-Driven Placer.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

MDiag: Mobility-assisted diagnosis for wireless sensor networks.
J. Netw. Comput. Appl., 2013

SRP: simultaneous routing and placement for congestion refinement.
Proceedings of the International Symposium on Physical Design, 2013

An efficient layout decomposition approach for triple patterning lithography.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Ripple 2.0: high quality routability-driven placement via global router integration.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Postplacement Voltage Island Generation.
ACM Trans. Design Autom. Electr. Syst., 2012

Postgrid Clock Routing for High Performance Microprocessor Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Construction of rectilinear Steiner minimum trees with slew constraints over obstacles.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Crosslink insertion for variation-driven clock network construction.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Placement and Routing for Cross-Referencing Digital Microfluidic Biochips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Simultaneous Handling of Symmetry, Common Centroid, and General Placement Constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

MSV-Driven Floorplanning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

On the Construction of Optimal Obstacle-Avoiding Rectilinear Steiner Minimum Trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Grid-to-ports clock routing for high performance microprocessor designs.
Proceedings of the 2011 International Symposium on Physical Design, 2011

Ripple: An effective routability-driven placer by iterative cell movement.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

A monte-carlo floating-point unit for self-validating arithmetic.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

An optimal algorithm for layer assignment of bus escape routing on PCBs.
Proceedings of the 48th Design Automation Conference, 2011

An exact algorithm for the construction of rectilinear Steiner minimum trees among complex obstacles.
Proceedings of the 48th Design Automation Conference, 2011

A provably good approximation algorithm for Rectangle Escape Problem with application to PCB routing.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Complexity of 3-D floorplans by analysis of graph cuboidal dual hardness.
ACM Trans. Design Autom. Electr. Syst., 2010

Multivoltage Floorplan Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Droplet-routing-aware module placement for cross-referencing biochips.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Physical synthesis of bus matrix for high bandwidth low power on-chip communications.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Practical placement and routing techniques for analog circuit designs.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Local clock skew minimization using blockage-aware mixed tree-mesh clock network.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Obstacle-avoiding rectilinear Steiner minimum tree construction: An optimal approach.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

CrossRouter: a droplet router for cross-referencing digital microfluidic biochips.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Fixed-outline thermal-aware 3D floorplanning.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

A dual-MST approach for clock network synthesis.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Congestion prediction in early stages of physical design.
ACM Trans. Design Autom. Electr. Syst., 2009

Block flipping and white space distribution for wirelength minimization.
Integr., 2009

Handling routability in floorplan design with twin binary trees.
Integr., 2009

Multi-voltage floorplan design with optimal voltage assignment.
Proceedings of the 2009 International Symposium on Physical Design, 2009

Generation of optimal obstacle-avoiding rectilinear Steiner minimum tree.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Analog placement with common centroid and 1-D symmetry constraints.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Floorplan Representations.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Global Interconnect Planning.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Slicing Floorplan Orientation.
Proceedings of the Encyclopedia of Algorithms - 2008 Edition, 2008

Optimizing wirelength and routability by searching alternative packings in floorplanning.
ACM Trans. Design Autom. Electr. Syst., 2008

Multi-bend bus driven floorplanning.
Integr., 2008

3-D floorplanning using labeled tree and dual sequences.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Network flow-based power optimization under timing constraints in MSV-driven floorplanning.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Obstacle-avoiding rectilinear Steiner tree construction.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

TCG-based multi-bend bus driven floorplanning.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Area reduction by deadspace utilization on interconnect optimized floorplan.
ACM Trans. Design Autom. Electr. Syst., 2007

Wire Retiming Problem With Net Topology Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Test scheduling for built-in self-tested embedded SRAMs with data retention faults.
IET Comput. Digit. Tech., 2007

Analog placement with common centroid constraints.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Voltage island-driven floorplanning.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

2006
Analog placement with symmetry and other placement constraints.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Post-placement voltage island generation.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Block alignment in 3D floorplan using layered TCG.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Shuttle mask floorplanning with modified alpha-restricted grid.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Retention-Aware Test Scheduling for BISTed Embedded SRAMs.
Proceedings of the 11th European Test Symposium, 2006

Optimal cell flipping in placement and floorplanning.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Congestion prediction in early stages.
Proceedings of the Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), 2005

Congestion prediction in floorplanning.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Placement constraints in floorplan design.
IEEE Trans. Very Large Scale Integr. Syst., 2004

Nonrectangular shaping and sizing of soft modules for floorplan-design improvement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Performance-driven register insertion in placement.
Proceedings of the 2004 International Symposium on Physical Design, 2004

2003
Slicing floorplan with clustering constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Twin binary sequences: a nonredundant representation for general nonslicing floorplan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Routability-driven floorplanner with buffer block planning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Temporal logic replication for dynamically reconfigurable FPGA partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Retiming with Interconnect and Gate Delay.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Clustering based acyclic multi-way partitioning.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees.
Proceedings of the 2003 Design, 2003

Fast buffer planning and congestion optimization in interconnect-driven floorplanning.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Interconnect-driven floorplanning by searching alternative packings.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
A Unified Method to Handle Different Kinds of Placement Constraints in Floorplan Design.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Twin binary sequences: a non-redundant representation for general non-slicing floorplan.
Proceedings of 2002 International Symposium on Physical Design, 2002

Congestion Estimation with Buffer Planning in Floorplan Design.
Proceedings of the 2002 Design, 2002

Non-Rectangular Shaping and Sizing of Soft Modules in Floorplan Design.
Proceedings of the 2002 Design, 2002

2001
On extending slicing floorplan to handle L/T-shaped modules andabutment constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Handling soft modules in general nonslicing floorplan usingLagrangian relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Slicing floorplan with clustering constraints.
Proceedings of ASP-DAC 2001, 2001

2000
Slicing floorplans with range constraint.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Floorplan area minimization using Lagrangian relaxation.
Proceedings of the 2000 International Symposium on Physical Design, 2000

1999
Slicing floorplans with boundary constraints.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Generation of Universal Series-Parallel Boolean Functions.
J. ACM, 1999

Slicing floorplans with range constraint.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Integrated floorplanning and interconnect planning.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Slicing Floorplans with Boundary Constraint.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
Slicing floorplans with pre-placed modules.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
How good are slicing floorplans?
Integr., 1997

On the Construction of Universal Series-Parallel Functions for Logic Module Design.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997


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