Charles J. Alpert

According to our database1, Charles J. Alpert authored at least 121 papers between 1993 and 2018.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2006, "For contributions to physical design automation of very large scale integrated (VLSI) circuits.".

Timeline

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Article 
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Links

On csauthors.net:

Bibliography

2018
MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Prim-Dijkstra Revisited: Achieving Superior Timing-driven Routing Trees.
Proceedings of the 2018 International Symposium on Physical Design, 2018

2017
Stitch aware detailed placement for multiple E-beam lithography.
Integr., 2017

Modern Challenges in Constructing Clocks.
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

2015
Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014
Techniques for scalable and effective routability evaluation.
ACM Trans. Design Autom. Electr. Syst., 2014

Pacman: driving nonuniform clock grid loads for low-skew robust clock network.
Proceedings of the ACM/IEEE International Workshop on System Level Interconnect Prediction, 2014

2013
Structure-Aware Placement Techniques for Designs With Datapaths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Clock power minimization using structured latch templates and decision tree induction.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

ICCAD-2013 CAD contest in placement finishing and benchmark suite.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

CATALYST: planning layer directives for effective design closure.
Proceedings of the Design, Automation and Test in Europe, 2013

Routing congestion estimation with real design constraints.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Keep it straight: teaching placement how to better handle designs with datapaths.
Proceedings of the International Symposium on Physical Design, 2012

MAPLE: multilevel adaptive placement for mixed-size designs.
Proceedings of the International Symposium on Physical Design, 2012

ICCAD-2012 CAD contest in design hierarchy aware routability-driven placement and benchmark suite.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Placement: Hot or Not?
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

WRIP: logic restructuring techniques for wirelength-driven incremental placement.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

GLARE: global and local wiring aware routability evaluation.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

The DAC 2012 routability-driven placement contest and benchmark suite.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Guiding a physical design closure system to produce easier-to-route designs with more predictable timing.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Shedding Physical Synthesis Area Bloat.
VLSI Design, 2011

Physical Synthesis with Clock-Network Optimization for Large Systems on Chips.
IEEE Micro, 2011

Quantifying academic placer performance on custom designs.
Proceedings of the 2011 International Symposium on Physical Design, 2011

The ISPD-2011 routability-driven placement contest and benchmark suite.
Proceedings of the 2011 International Symposium on Physical Design, 2011

2010
Speeding Up Physical Synthesis with Transactional Timing Analysis.
IEEE Des. Test Comput., 2010

ITOP: integrating timing optimization within placement.
Proceedings of the 2010 International Symposium on Physical Design, 2010

Ultra-fast interconnect driven cell cloning for minimizing critical path delay.
Proceedings of the 2010 International Symposium on Physical Design, 2010

What makes a design difficult to route.
Proceedings of the 2010 International Symposium on Physical Design, 2010

New placement prediction and mitigation techniques for local routing congestion.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Design-hierarchy aware mixed-size placement for routability optimization.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Detecting tangled logic structures in VLSI netlists.
Proceedings of the 47th Design Automation Conference, 2010

2009
A Fully Polynomial-Time Approximation Scheme for Timing-Constrained Minimum Cost Layer Assignment.
IEEE Trans. Circuits Syst. II Express Briefs, 2009

Ispd2009 clock network synthesis contest.
Proceedings of the 2009 International Symposium on Physical Design, 2009

A faster approximation scheme for timing driven minimum cost layer assignment.
Proceedings of the 2009 International Symposium on Physical Design, 2009

CRISP: Congestion reduction by iterated spreading during placement.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion.
Proceedings of the 46th Design Automation Conference, 2009

2008
Introduction to Physical Design.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Placement-Driven Synthesis Design Closure Tool.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Fast interconnect synthesis with layer assignment.
Proceedings of the 2008 International Symposium on Physical Design, 2008

Pyramids: an efficient computational geometry-based approach for timing-driven placement.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A polynomial time approximation scheme for timing constrained minimum cost layer assignment.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Path smoothing via discrete optimization.
Proceedings of the 45th Design Automation Conference, 2008

2007
Path-Based Buffer Insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Diffusion-Based Placement Migration With Application on Legalization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fast Algorithms for Slew-Constrained Minimum Cost Buffering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Techniques for Fast Physical Synthesis.
Proc. IEEE, 2007

The nuts and bolts of physical synthesis.
Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

Probabilistic Congestion Prediction with Partial Blockages.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

The coming of age of physical synthesis.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

RQL: Global Placement via Relaxed Quadratic Spreading and Linearization.
Proceedings of the 44th Design Automation Conference, 2007

Hippocrates: First-Do-No-Harm Detailed Placement.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Fast Electrical Correction Using Resizing and Buffering.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

ISPD 2005/2006 Placement Benchmarks.
Proceedings of the Modern Circuit Placement, Best Practices and Results, 2007

2006
A Fast Hierarchical Quadratic Placement Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Accurate estimation of global buffer delay within a floorplan.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Timing-driven Steiner trees are (practically) free.
Proceedings of the 43rd Design Automation Conference, 2006

2005
An efficient surface-based low-power buffer insertion algorithm.
Proceedings of the 2005 International Symposium on Physical Design, 2005

The ISPD2005 placement contest and benchmark suite.
Proceedings of the 2005 International Symposium on Physical Design, 2005

A semi-persistent clustering technique for VLSI circuit placement.
Proceedings of the 2005 International Symposium on Physical Design, 2005

Practical techniques to reduce skew and its variations in buffered clock networks.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Computational geometry based placement migration.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Diffusion-based placement migration.
Proceedings of the 42nd Design Automation Conference, 2005

Making fast buffer insertion even faster via approximation techniques.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Placement stability metrics.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A delay metric for RC circuits based on the Weibull distribution.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Closed-form delay and slew metrics made easy.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Porosity-aware buffered Steiner tree construction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

A fast algorithm for identifying good buffer insertion candidate locations.
Proceedings of the 2004 International Symposium on Physical Design, 2004

Fast and flexible buffer trees that navigate the physical layout environment.
Proceedings of the 41th Design Automation Conference, 2004

A place and route aware buffered Steiner tree construction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

Complexity analysis and speedup techniques for optimal buffer insertion with minimum cost.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Buffer insertion with adaptive blockage avoidance.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Optimal path routing in single- and multiple-clock domain systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Guest editorial.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Effective free space management for cut-based placement via analytical constraint generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Minimum buffered routing with bounded capacitive load for slew rate and reliability control.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A practical methodology for early buffer and wire resource allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Closed form expressions for extending step delay and slew metrics to ramp inputs.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Porosity aware buffered steiner tree construction.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Delay and slew metrics using the lognormal distribution.
Proceedings of the 40th Design Automation Conference, 2003

2002
Correction to "interconnect synthesis without wire tapering".
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Probability-driven routing in a datapath environment.
Integr., 2002

PERI: a technique for extending delay and slew metrics to ramp inputs.
Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Optimal buffered routing path constructions for single and multiple clock domain systems.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

Free space management for cut-based placement.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Steiner tree optimization for buffers, blockages, and bays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

RC delay metrics for performance optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Interconnect synthesis without wire tapering.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Buffered Steiner trees for difficult instances.
Proceedings of the 2001 International Symposium on Physical Design, 2001

Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000
Hypergraph partitioning with fixed vertices [VLSI CAD].
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Datapath routing based on a decongestion metric.
Proceedings of the 2000 International Symposium on Physical Design, 2000

A two moment RC delay metric for performance optimization.
Proceedings of the 2000 International Symposium on Physical Design, 2000

An "Effective" Capacitance Based Delay Metric for RC Interconnect.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Analytical Engines are Unnecessary in Top-down Partitioning-based Placement.
VLSI Design, 1999

Buffer insertion for noise and delay optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Spectral Partitioning with Multiple Eigenvectors.
Discret. Appl. Math., 1999

Partitioning with terminals: a "new" problem and new benchmarks.
Proceedings of the 1999 International Symposium on Physical Design, 1999

Is wire tapering worthwhile?
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Buffer Insertion with Accurate Gate and Interconnect Delay Computation.
Proceedings of the 36th Conference on Design Automation, 1999

1998
Multilevel circuit partitioning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Faster minimization of linear wirelength for global placement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

The ISPD98 circuit benchmark suite.
Proceedings of the 1998 International Symposium on Physical Design, 1998

1997
Faster minimization of linear wirelength for global placement.
Proceedings of the 1997 International Symposium on Physical Design, 1997

Wire Segmenting for Improved Buffer Insertion.
Proceedings of the 34st Conference on Design Automation, 1997

Quadratic Placement Revisited.
Proceedings of the 34st Conference on Design Automation, 1997

1996
A general framework for vertex orderings with applications to circuit clustering.
IEEE Trans. Very Large Scale Integr. Syst., 1996

1995
Multiway partitioning via geometric embeddings, orderings, and dynamic programming.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Prim-Dijkstra tradeoffs for improved performance-driven routing tree design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Recent directions in netlist partitioning: a survey.
Integr., 1995

Spectral Partitioning: The More Eigenvectors, The Better.
Proceedings of the 32st Conference on Design Automation, 1995

1994
A general framework for vertex orderings, with applications to netlist clustering.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Multi-Way Partitioning Via Spacefilling curves and Dynamic Programming.
Proceedings of the 31st Conference on Design Automation, 1994

1993
A Direct Combination of the Prim and Dijkstra Constructions for Improved Performance-driven Global Routing.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Minimum Density Interconneciton Trees.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

Geometric Embeddings for Faster and Better Multi-Way Netlist Partitioning.
Proceedings of the 30th Design Automation Conference. Dallas, 1993


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