Wang Liao

Orcid: 0000-0003-2134-5588

Affiliations:
  • Kochi University of Technology, Department of Engineering, Kami, Japan
  • Osaka University, School of Systems Engineering, Japan (PhD 2019)


According to our database1, Wang Liao authored at least 13 papers between 2017 and 2025.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
Genshin: A Generalized Framework with Software-Hardware Co-design and Pruned Fault Injection for Reliability Analysis.
Proceedings of the IEEE International Test Conference, 2025

HachiFI: A Lightweight SoC Architecture-Independent Fault-Injection Framework for SEU Impact Evaluation.
Proceedings of the Design, Automation & Test in Europe Conference, 2025

2024
How accurately can soft error impact be estimated in black-box/white-box cases? - a case study with an edge AI SoC -.
Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

2023
Characterizing SEU Cross Sections of 12- and 28-nm SRAMs for 6.0, 8.0, and 14.8 MeV Neutrons.
Proceedings of the IEEE International Reliability Physics Symposium, 2023

2021
Development of Autonomous Driving System based on Image Recognition using Programmable SoCs.
Proceedings of the International Conference on Field-Programmable Technology, 2021

2020
Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

Impact of Hydrided and Non-Hydrided Materials Near Transistors on Neutron-Induced Single Event Upsets.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

When Single Event Upset Meets Deep Neural Networks: Observations, Explorations, and Remedies.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

Soft Error and Its Countermeasures in Terrestrial Environment.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Analyzing Impacts of SRAM, FF and Combinational Circuit on Chip-Level Neutron-Induced Soft Error Rate.
IEICE Trans. Electron., 2019

Negative and Positive Muon-Induced SEU Cross Sections in 28-nm and 65-nm Planar Bulk CMOS SRAMs.
Proceedings of the IEEE International Reliability Physics Symposium, 2019

Development of Autonomous Driving System Using Programmable SoCs.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2017
Contributions of SRAM, FF and combinational circuit to chip-level neutron-induced soft error rate: - Bulk vs. FD-SOI at 0.5 and 1.0V -.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017


  Loading...