Yukio Mitsuyama

According to our database1, Yukio Mitsuyama authored at least 45 papers between 1999 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
Development of Autonomous Driving System based on Image Recognition using Programmable SoCs.
Proceedings of the International Conference on Field-Programmable Technology, 2021

2020
Measurement of Variations in FPGAs under Various Load Conditions.
IPSJ Trans. Syst. LSI Des. Methodol., 2020

33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Characterizing Energetic Dependence of Low-Energy Neutron-induced MCUs in 65 nm bulk SRAMs.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

2019
Development of Autonomous Driving System Using Programmable SoCs.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
Via-Switch FPGA: Highly Dense Mixed-Grained Reconfigurable Architecture With Overlay Via-Switch Crossbars.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Sensor Signal Processing Using High-Level Synthesis With a Layered Architecture.
IEEE Embed. Syst. Lett., 2018

Design Flow and Design Tools.
Proceedings of the Principles and Structures of FPGAs., 2018

2016
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015
Reliability-configurable mixed-grained reconfigurable array compatible with high-level synthesis.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
NBTI Mitigation Method by Inputting Random Scan-In Vectors in Standby Time.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Comparative Evaluation of Lifetime Enhancement with Fault Avoidance on Dynamically Reconfigurable Devices.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Reliability-Configurable Mixed-Grained Reconfigurable Array Supporting C-Based Design and Its Irradiation Testing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

SET Pulse-Width Measurement Suppressing Pulse-Width Modulation and Within-Die Process Variation Effects.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Variability and Soft-Error Resilience in Dependable VLSI Platform.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013
Implementing Flexible Reliability in a Coarse-Grained Reconfigurable Architecture.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A Worst-Case-Aware Design Methodology for Noise-Tolerant Oscillator-Based True Random Number Generator With Stochastic Behavior Modeling.
IEEE Trans. Inf. Forensics Secur., 2013

Field Slack Assessment for Predictive Fault Avoidance on Coarse-Grained Reconfigurable Devices.
IEICE Trans. Inf. Syst., 2013

PVT-induced timing error detection through replica circuits and time redundancy in reconfigurable devices.
IEICE Electron. Express, 2013

Mixed-grained reconfigurable architecture supporting flexible reliability and C-based design.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

2012
Adaptive Performance Compensation With In-Situ Timing Error Predictive Sensors for Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Static voltage over-scaling and dynamic voltage variation tolerance with replica circuits and time redundancy in reconfigurable devices.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

A predictive delay fault avoidance scheme for coarse-grained reconfigurable architecture.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
Stress Probability Computation for Estimating NBTI-Induced Delay Degradation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Implications of Reliability Enhancement Achieved by Fault Avoidance on Dynamically Reconfigurable Architectures.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

2010
Transistor Variability Modeling and its Validation With Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Measurement Circuits for Acquiring SET Pulse Width Distribution with Sub-FO1-Inverter-Delay Resolution.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Design Procedure for Oscillator-Based Hardware Random Number Generator with Stochastic Behavior Modeling.
Proceedings of the Information Security Applications - 11th International Workshop, 2010

Comparative study on delay degrading estimation due to NBTI with circuit/instance/transistor-level stress probability consideration.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Measurement circuits for acquiring SET pulsewidth distribution with sub-FO1-inverter-delay resolution.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Adaptive performance control with embedded timing error predictive sensors for subthreshold circuits.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability.
IEICE Trans. Electron., 2009

Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Coarse-grained dynamically reconfigurable architecture with flexible reliability.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Adaptive performance compensation with in-situ timing error prediction for subthreshold circuits.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2008
Area-Efficient Reconfigurable Architecture for Media Processing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2005
Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2002
Burst mode: a new acceleration mode for 128-bit block ciphers.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
VLSI architecture of dynamically reconfigurable hardware-based cipher.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A dynamically reconfigurable hardware-based cipher chip.
Proceedings of ASP-DAC 2001, 2001

1999
FeRAM Circuit Technology for System on a Chip.
Proceedings of the 1st NASA / DoD Workshop on Evolvable Hardware (EH '99), 1999


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