Wei Cao

Orcid: 0000-0003-0339-7093

Affiliations:

Fudan University, State Key Laboratory of ASIC and System, Shanghai, China

According to our database¹, Wei Cao authored at least 31 papers between 2008 and 2024.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2024

Qubit-Wise Architecture Search Method for Variational Quantum Circuits.

[BibT_eX]

[DOI]

CoRR, 2024

2022

Acceleration of Rotated Object Detection on FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

2021

SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

MRI-based brain tumor segmentation using FPGA-accelerated neural network.

[BibT_eX]

[DOI]

BMC Bioinform., 2021

LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2021

A High-Precision Flexible Symmetry-Aware Architecture for Element-Wise Activation Functions.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2021

2020

A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2020

2019

RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2019

SpWMM: A High-Performance Sparse-Winograd Matrix-Matrix Multiplication Accelerator for CNNs.

[BibT_eX]

[DOI]

Di Wu

Wei Cao

Lingli Wang

Proceedings of the International Conference on Field-Programmable Technology, 2019

A High Performance FPGA-Based Accelerator Design for End-to-End Speaker Recognition System.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

Stream Processing Dual-Track CGRA for Object Inference.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

High Throughput CNN Accelerator Design Based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2018

A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

Accelerating low bit-width convolutional neural networks with embedded FPGA.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

High performance Deformable Part Model accelerator based on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A high performance FPGA-based accelerator for large-scale convolutional neural networks.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA.

[BibT_eX]

[DOI]

Yangjie Zhang

Wei Cao

Lingli Wang

Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2013

A hardware implementation of Bag of Words and Simhash for image recognition.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

An FPGA-cluster-accelerated match engine for content-based image retrieval.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

A reconfigurable floating-point FFT architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2011

A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A coarse-grained reconfigurable computing unit.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

A permutation network for configurable and scalable FFT processors.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2008

A high-performance reconfigurable VLSI architecture for vbsme in H.264.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2008

High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A high-performance reconfigurable 2-D transform architecture for H.264.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A novel dynamic reconfigurable VLSI architecture for H.264 transforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Wei Cao

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