Jiarong Tong

According to our database1, Jiarong Tong authored at least 29 papers between 1998 and 2013.

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Bibliography

2013
SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Optimisation of Fixed Polarity Canonical Or-Coincidence Expansions.
J. Comput., 2013

Yet Another Many-Objective Clustering (YAMO-Pack) for FPGA CAD.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Indirect connection aware attraction for FPGA clustering (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
A novel memristor-based rSRAM structure for multiple-bit upsets immunity.
IEICE Electron. Express, 2012

A partially reconfigurable architecture supporting hardware threads.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

2011
A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

Fault modeling and characteristics of SRAM-based FPGAs (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

A coarse-grained reconfigurable computing unit.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
Accelerating Boolean Matching Using Bloom Filter.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Engineering a scalable Boolean matching based on EDA SaaS 2.0.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

General switch box modeling and optimization for FPGA routing architectures.
Proceedings of the International Conference on Field-Programmable Technology, 2010

Building a faster boolean matcher using bloom filter.
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

2009
A delay-optimized universal FPGA routing architecture.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
A high-performance reconfigurable VLSI architecture for vbsme in H.264.
IEEE Trans. Consumer Electron., 2008

High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A high-performance reconfigurable 2-D transform architecture for H.264.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Variational capacitance modeling using orthogonal polynomial method.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
Proceedings of the 45th Design Automation Conference, 2008

Design and implementation of the configuration circuit for FDP FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

A novel dynamic reconfigurable VLSI architecture for H.264 transforms.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2005
Domain Specific Non-Uniform Routing Architecture for Embedded Programmable IP Core (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004
Frequency domain wavelet method with GMRES for large-scale linear circuit simulation.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Two-sided projection method in variational equation model order reduction of nonlinear circuits.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003
A SC-based novel configurable analog cell.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

1999
An Analytical Delay Model for SRAM-Based FPGA Interconnections.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999

1998
FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm.
Proceedings of the ASP-DAC '98, 1998


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