Chung-Han Chou

According to our database, Chung-Han Chou authored at least 13 papers between 2010 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Invited Paper: 2023 ICCAD CAD Contest Problem A: Multi-Bit Large-Scale Boolean Matching.

Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu, Kei-Yong Khoo

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

2022

2022 CAD Contest Problem A: Learning Arithmetic Operations from Gate-Level Circuit.

Chung-Han Chou, Chih-Jen (Jacky) Hsu, Chi-An (Rocky) Wu, Kuan-Hua Tu

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021

2021 CAD Contest Problem A: Functional ECO with Behavioral Change Guidance Invited Paper.

Yen-Chun Fang, Shao-Lun Huang, Chi-An Wu, Chung-Han Chou, Chih-Jen Hsu, WoeiTzy Jong, Kei-Yong Khoo

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

2020

Making Aging Useful by Recycling Aging-induced Clock Skew.

Tien-Hung Tseng, Chung-Han Chou, Kai-Chiang Wu

ACM Trans. Design Autom. Electr. Syst., 2020

2019

Aging-aware chip health prediction adopting an innovative monitoring strategy.

Yun-Ting Wang, Kai-Chiang Wu, Chung-Han Chou, Shih-Chieh Chang

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Sensor-Based Time Speculation in the Presence of Timing Variability.

Chung-Han Chou, Tsui-Yun Chang, Kai-Chiang Wu, Shih-Chieh Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

2017

Ping-Pong Mesh: A New Resonant Clock Design for Surge Current and Area Overhead Reduction.

Chung-Han Chou, Yenting Lai, Yi-Chun Chang, Chih-Yu Wang, Liang-Chia Cheng, Shih-Hsu Huang, Shih-Chieh Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

CN-SIM: A cycle-accurate full system power delivery noise simulator.

Kassan Unda, Chung-Han Chou, Shih-Chieh Chang, Cheng Zhuo, Yiyu Shi

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs.

Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang

IEEE Trans. Very Large Scale Integr. Syst., 2016

2013

On the futility of thermal through-silicon-vias.

Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Yiyu Shi, Jui-Hung Chien, Shih-Chieh Chang

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Low-power timing closure methodology for ultra-low voltage designs.

Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

2011

On the preconditioner of conjugate gradient method - A power grid simulation perspective.

Chung-Han Chou, Nien-Yu Tsai, Hao Yu, Che-Rung Lee, Yiyu Shi, Shih-Chieh Chang

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Clock skew optimization considering complicated power modes.

Chiao-Ling Lung, Zi-Yi Zeng, Chung-Han Chou, Shih-Chieh Chang

Proceedings of the Design, Automation and Test in Europe, 2010