Wen-Zen Shen

According to our database, Wen-Zen Shen authored at least 24 papers between 1990 and 2001.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2001

Grouped input power sensitive transition an input sequence compaction technique for power estimation.

Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A pattern compaction technique for power estimation based on power sensitivity information.

Chih-Yang Hsu, Chaur-Wen Wei, Wen-Zen Shen

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

2000

ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen

IEEE Trans. Very Large Scale Integr. Syst., 2000

A new method for constructing IP level power model based on power sensitivity.

Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou

Proceedings of ASP-DAC 2000, 2000

1999

A structure-oriented power modeling technique for macrocells.

Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou

IEEE Trans. Very Large Scale Integr. Syst., 1999

1998

On circuit clustering for area/delay tradeoff under capacity and pin constraints.

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang

IEEE Trans. Very Large Scale Integr. Syst., 1998

1997

A power modeling and characterization method for macrocells using structure information.

Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits.

Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu

Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997

1996

A power modeling and characterization method for the CMOS standard cell library.

Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.

Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping.

Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao

Proceedings of the 32st Conference on Design Automation, 1995

Fanout fault analysis for digital logic circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Transistor reordering rules for power reduction in CMOS gates.

Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1994

On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design.

Wen-Zen Shen, Yi-Hsin Tao, Lan-Rong Dung

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A cell-based power estimation in CMOS combinational circuits.

Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1993

Restructuring and logic minimization for testable PLA.

Gwo-Haur Hwang, Wen-Zen Shen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Design of Pseudoexhaustive Testable PLA with Low Overhead.

Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan

IEEE Trans. Computers, 1993

1992

MT-SIM a mixed-level transition fault simulator based on parallel patterns.

Chung Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang

J. Electron. Test., 1992

SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence.

Ching Ping Wu, Chung Len Lee, Wen-Zen Shen

Proceedings of the conference on European design automation, 1992

Coalgebraic Division for Multilevel Logic Synthesis.

Wen-Jun Hsu, Wen-Zen Shen

Proceedings of the 29th Design Automation Conference, 1992

1991

Single-fault fault-collapsing analysis in sequential logic circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Checkpoints in irredundant two-level combinational circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen

J. Electron. Test., 1991

1990

A Parallel Pattern Mixed-Level Fault Simulator.

Tyh-Song Hwang, Chung Len Lee, Wen-Zen Shen, Ching Ping Wu

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990