Jwu E. Chen

According to our database, Jwu E. Chen authored at least 53 papers between 1991 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Prediction of the Test Yield of Future Integrated Circuits Through the Deductive Estimation Method.

Chung-Huang Yeh, Jwu E. Chen

J. Circuits Syst. Comput., August, 2023

Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments.

Chung-Huang Yeh, Jwu E. Chen

IEEE Des. Test, June, 2023

Multiple Retest Systems for Screening High-Quality Chips.

Chung-Huang Yeh, Jwu E. Chen

J. Electron. Test., April, 2023

2022

Application of Three-Repetition Tests Scheme to Improve Integrated Circuits Test Quality to Near-Zero Defect.

Chung-Huang Yeh, Jwu E. Chen

Sensors, 2022

2021

Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling.

Leon Li-Yang Chen, Katherine Shu-Min Li, Xu-Hao Jiang, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu

Proceedings of the IEEE International Test Conference, 2021

Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering.

Katherine Shu-Min Li, Leon Li-Yang Chen, Ken Chau-Cheung Cheng, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Nova Cheng-Yen Tsai, Leon Chou, Gus Chang-Hung Han, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu

Proceedings of the 26th IEEE European Test Symposium, 2021

2020

Innovative Practice on Wafer Test Innovations.

Dyi-Chung Hu, Hirohito Hashimoto, Li-Fong Tseng, Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Sying-Jyan Wang, Sean Y.-S. Chen, Jwu E. Chen, Clark Liu, Andrew Yi-Ann Huang

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

The Decision Mechanism Uses the Multiple-Tests Scheme to Improve Test Yield in IC Testing.

Chung-Huang Yeh, Jwu E. Chen

Proceedings of the IEEE International Test Conference in Asia, 2020

Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis.

Ken Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019

Repeated Testing Applications for Improving the IC Test Quality to Achieve Zero Defect Product Requirements.

Chung-Huang Yeh, Jwu E. Chen

J. Electron. Test., 2019

2009

A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

IEEE Trans. Very Large Scale Integr. Syst., 2009

2007

Multilevel Full-Chip Routing With Testability and Yield Enhancement.

Katherine Shu-Min Li, Yao-Wen Chang, Chung-Len Lee, Chauchin Su, Jwu E. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

J. Electron. Test., 2007

2006

IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults.

Katherine Shu-Min Li, Chauchin Su, Yao-Wen Chang, Chung-Len Lee, Jwu E. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu

Proceedings of the 2006 IEEE International Test Conference, 2006

2005

Adaptive Encoding Scheme for Test Volume/Time Reduction in SoC Scan Testing.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

A Scan Matrix Design for Low Power Scan-Based Test.

Shih Ping Lin, Chung-Len Lee, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Finite State Machine Synthesis for At-Speed Oscillation Testability.

Katherine Shu-Min Li, Chung-Len Lee, Tagin Jiang, Chauchin Su, Jwu E. Chen

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

Oscillation ring based interconnect test scheme for SOC.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-Micron VLSI.

Katherine Shu-Min Li, Chung-Len Lee, Chauchin Su, Jwu E. Chen

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

A New BIST Scheme Based on a Summing-into-Timing-Signal Principle with Self Calibration for the DAC.

Guan-Xun Chen, Chung-Len Lee, Jwu E. Chen

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits.

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen

J. Inf. Sci. Eng., 2003

2002

Structural Fault Based Specification Reduction for Testing Analog Circuits.

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen

J. Electron. Test., 2002

An Efficient Test and Diagnosis Scheme for the Feedback Type of Analog Circuits with Minimal Added Circuits.

Jun-Weir Lin, Chung-Len Lee, Jwu E. Chen

Proceedings of the 2002 Design, 2002

A Testing Scheme for Crosstalk Faults Based on the Oscillation Test Signal.

Ming Shae Wu, Chung-Len Lee, Chi Peng Chang, Jwu E. Chen

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Fault Diagnosis for Linear Analog Circuits.

Jun-Weir Lin, Chung-Len Lee, Chauchin Su, Jwu E. Chen

J. Electron. Test., 2001

Guardband Determination for the Detection of Off-State and Junction Leakages in DRAM Testing.

Mill-Jer Wang, R.-L. Jiang, J.-W. Hsia, Chih-Hu Wang, Jwu E. Chen

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

A Behavior-Level Fault Model for the Closed-Loop Operational Amplifier.

Yeong-Jar Chang, Chung-Len Lee, Jwu E. Chen, Chauchin Su

J. Inf. Sci. Eng., 2000

Oscillation Ring Delay Test for High Performance Microprocessors.

Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir

J. Electron. Test., 2000

Is IDDQ testing not applicable for deep submicron VLSI in year 2011?

Chih-Wen Lu, Chauchin Su, Chung-Len Lee, Jwu E. Chen

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A case study of failure analysis and guardband determination for a 64M-bit DRAM.

Chin-Te Kao, Sam Wu, Jwu E. Chen

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

A methodology for fault model development for hierarchical linear systems.

Yin-Chao Huang, Chung-Len Lee, Jun-Weir Lin, Jwu E. Chen, Chauchin Su

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

A Compiled-Code Parallel Pattern Logic Simulator With Inertial Delay Model.

Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen

J. Inf. Sci. Eng., 1999

A DFT for semi-DC fault diagnosis for switched-capacitor circuits.

Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang, Jwu E. Chen

Proceedings of the 4th European Test Workshop, 1999

1998

A Two-Phase Fault Simulation Scheme for Sequential Circuits.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen

J. Inf. Sci. Eng., 1998

Partial Reset and Scan for Flip-Flops Based on States Requirement for Test Generation.

Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Maximization of power dissipation under random excitation for burn-in testing.

Kuo-Chan Huang, Chung-Len Lee, Jwu E. Chen

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997

Identifying invalid states for sequential circuit test generation.

Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Functional test pattern generation for CMOS operational amplifier.

Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

Fault diagnosis of odd-even sorting networks.

Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

Invalid State Identification for Sequential Circuit Test Generation.

Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

Yield Improvement by Test Error Cancellation.

Jwu E. Chen

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Identifying Untestable Faults in Sequential Circuits.

Hsing-Chung Liang, Chung-Len Lee, Jwu E. Chen

IEEE Des. Test Comput., 1995

Factorization of Multi-Valued Logic Functions.

Hui Min Wang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

Identification of robust untestable path delay faults.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

Fanout fault analysis for digital logic circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Complete Test Set for Multiple-Valued Logic Networks.

Hui Min Wang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Algebraic Division for Multilevel Logic Synthesis of Multi-Valued Logic Circuits.

Hui Min Wang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning.

Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

TRANS: A Fast and Memory-Efficient Path Delay Fault Simulator.

Meng Chiy Lin, Jwu E. Chen, Chung-Len Lee

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1992

Fault Analysis on Two-Level (K+1)-Valued Logic Circuits.

Hui Min Wang, Chung-Len Lee, Jwu E. Chen

Proceedings of the 22nd IEEE International Symposium on Multiple-Valued Logic, 1992

1991

Single-fault fault-collapsing analysis in sequential logic circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Checkpoints in irredundant two-level combinational circuits.

Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen

J. Electron. Test., 1991