Wenda Zhao

Orcid: 0000-0002-1834-646X

Affiliations:
  • University of Texas at Austin, Austin, TX, USA


According to our database1, Wenda Zhao authored at least 20 papers between 2019 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Online presence:

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Bibliography

2023
A 26.4mW, 18.6MS/s Image Reconstruction Processor for IoT Compressive Sensing.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2021
A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing.
IEEE J. Solid State Circuits, 2021

A 77.1-dB-SNDR 6.25-MHz-BW Pipeline SAR ADC With Enhanced Interstage Gain Error Shaping and Quantization Noise Shaping.
IEEE J. Solid State Circuits, 2021

10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021

An 81.5dB-DR 1.25MHz-BW VCO-Based CT ΔΣ ADC with Double-PFD Quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
A Second-Order Purely VCO-Based CT ΔΣ ADC Using a Modified DPLL Structure in 40-nm CMOS.
IEEE J. Solid State Circuits, 2020

A 0.025-mm<sup>2</sup> 0.8-V 78.5-dB SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL- ΔΣ M Structure.
IEEE J. Solid State Circuits, 2020

A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier.
IEEE J. Solid State Circuits, 2020

An Energy-Efficient Time-Domain Incremental Zoom Capacitance-to-Digital Converter.
IEEE J. Solid State Circuits, 2020

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique.
IEEE J. Solid State Circuits, 2020

A 13-bit 0.005-mm<sup>2</sup> 40-MS/s SAR ADC With kT/C Noise Cancellation.
IEEE J. Solid State Circuits, 2020

An Always-on 4× Compressive VGA CMOS Imager with 51pJ/Pixel and >32dB PSNR.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

16.5 A 13b 0.005mm<sup>2</sup> 40MS/s SAR ADC with kT/C Noise Cancellation.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

A 77.1-dB 6.25-MHz-BW Pipeline SAR ADC with Enhanced Interstage Gain Error Shaping and Quantization Error Shaping.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A Two-Step ADC With a Continuous-Time SAR-Based First Stage.
IEEE J. Solid State Circuits, 2019

A 16fJ/Conversion-Step Time-Domain Two-Step Capacitance-to-Digital Converter.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 0.01mm<sup>2</sup> 25µW 2MS/s 74dB-SNDR Continuous-Time Pipelined-SAR ADC with 120fF Input Capacitor.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

A 10b 120MS/s SAR ADC with Reference Ripple Cancellation Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 0.025-mm<sup>2</sup> 0.8-V 78.5dB-SNDR VCO-Based Sensor Readout Circuit in a Hybrid PLL-ΔΣM Structure.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019


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