Will R. Moore

According to our database1, Will R. Moore authored at least 15 papers between 1986 and 2007.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2007
Extending gate-level diagnosis tools to CMOS intra-gate faults.
IET Comput. Digit. Tech., 2007

2006
A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

2005
A novel stuck-at based method for transistor stuck-open fault diagnosis.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Stuck-open fault diagnosis with stuck-at model.
Proceedings of the 10th European Test Symposium, 2005

2000
Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1998
Implications of Voltage and Dimension Scaling on CMOS Testing: The Multidimensional Testing Paradigm.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

1995
Testing VLSI regular arrays.
J. Electron. Test., 1995

1993
Multiple Fault Diagnosis in Printed Circuit Boards.
Proceedings of the Proceedings IEEE International Test Conference 1993, Designing, Testing, and Diagnostics, 1993

1990
Silicon models of associative learning in <i>Aplysia</i>.
Neural Networks, 1990

Testing a motion estimator array.
Proceedings of the Application Specific Array Processors, 1990

1989
Vlsi Devices and Circuits for Neural Networks.
Int. J. Neural Syst., 1989

A semantic network architecture for artificial intelligence processing.
Proceedings of the IEEE International Workshop on Tools for Artificial Intelligence: Architectures, 1989

Imperfectly connected 2D arrays for image processing.
Proceedings of the Nineteenth International Symposium on Fault-Tolerant Computing, 1989

1988
Parallel architectures for AI semantic network processing.
Knowl. Based Syst., 1988

1986
A review of fault-tolerant techniques for the enhancement of integrated circuit yield.
Proc. IEEE, 1986


  Loading...