Guido Gronthoud

According to our database1, Guido Gronthoud authored at least 24 papers between 2000 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2012
ADC Multi-Site Test Based on a Pre-test with Digital Input Stimulus.
J. Electron. Test., 2012

2009
Algorithms for ADC Multi-site Test with Digital Input Stimulus.
Proceedings of the 14th IEEE European Test Symposium, 2009

2008
Analog Test Bus Infrastructure for RF/AMS Modules in Core-Based Design.
Proceedings of the 13th European Test Symposium, 2008

2007
Extending gate-level diagnosis tools to CMOS intra-gate faults.
IET Comput. Digit. Tech., 2007

Modeling Power Supply Noise in Delay Testing.
IEEE Des. Test Comput., 2007

On Performance Testing with Path Delay Patterns.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Re-configuration of sub-blocks for effective application of time domain tests.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Structural Fault Modeling and Fault Detection Through Neyman-Pearson Decision Criteria for Analog Integrated Circuits.
J. Electron. Test., 2006

A Gate-Level Method for Transistor-Level Bridging Fault Diagnosis.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Power Supply Noise in Delay Testing.
Proceedings of the 2006 IEEE International Test Conference, 2006

2005
Multi-VDD Testing for Analog Circuits.
J. Electron. Test., 2005

A New Algorithm for Dynamic Faults Detection in RAMs.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Functional vs. multi-VDD testing of RF circuits.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A novel stuck-at based method for transistor stuck-open fault diagnosis.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Stuck-open fault diagnosis with stuck-at model.
Proceedings of the 10th European Test Symposium, 2005

Memory testing improvements through different stress conditions.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

Memory Testing Under Different Stress Conditions: An Industrial Evaluation.
Proceedings of the 2005 Design, 2005

2004
On Hazard-free Patterns for Fine-delay Fault Testing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Power Supply Ramping for Quasi-static Testing of PLLs.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

VDD Ramp Testing for RF Circuits.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Process-variability aware delay fault testing of ΔV<sub>T</sub> and weak-open defects.
Proceedings of the 8th European Test Workshop, 2003

2001
Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design.
Proceedings of the 6th European Test Workshop, 2001

2000
Delay-fault testing and defects in deep sub-micron ICs-does critical resistance really mean anything?
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000


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