Woo-Seung Yang

According to our database1, Woo-Seung Yang authored at least 8 papers between 1997 and 2005.

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Bibliography

2005
Conscep: a Configurable Soc Emulation Platform for C-based Fast Prototyping.
J. Circuits Syst. Comput., 2005

Simulation acceleration of transaction-level models for SoC with RTL sub-blocks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Communication-efficient hardware acceleration for fast functional simulation.
Proceedings of the 41th Design Automation Conference, 2004

2003
Signal Scheduling Driven Circuit Partitioning for Multiple FPGAs with Time-multiplexed Interconnection.
Proceedings of the IFIP VLSI-SoC 2003, 2003

2001
Low-power high-level synthesis using latches.
Proceedings of ASP-DAC 2001, 2001

2000
Multi-thread VLIW processor architecture for HDTV decoding.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1997
A C-Based RTL Design Verification Methodology for Complex Microprocessor.
Proceedings of the 34st Conference on Design Automation, 1997

Verification methodology of compatible microprocessors.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997


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