Xianting Su
Orcid: 0009-0009-1403-7094
According to our database1,
Xianting Su
authored at least 5 papers
between 2024 and 2025.
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Bibliography
2025
Load-driven inductive peaking design for broad band continuous-time linear equalizer.
Microelectron. J., 2025
A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units.
Microelectron. J., 2025
2024
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor.
IEEE J. Solid State Circuits, November, 2024
A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers.
Proceedings of the IEEE International Conference on Integrated Circuits, 2024
A 0.0006-mm<sup>2</sup> 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024