Xianting Su

According to our database, Xianting Su authored at least 8 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2026

A 0.0006-mm², 0.13-pJ/bit, 9-21-Gb/s Sub-Sampling CDR With Inverter-Based Frequency Multiplier and Embedded 1:3 DEMUX in 65-nm CMOS.

Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Depeng Sun, Shubin Liu, Zhangming Zhu

IEEE J. Solid State Circuits, May, 2026

2025

Load-driven inductive peaking design for broad band continuous-time linear equalizer.

Miao Zhang, Ruidong Li, Xiaoteng Zhao, Xianting Su, Zhicheng Dong, Zekai Yang, Hongyu Su, Hongzhi Liang, Yukui Yu, Shubin Liu

Microelectron. J., 2025

Withdrawal notice to "A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator" [Microelectron. J. 166 (2025) 106872].

Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu

Microelectron. J., 2025

A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator.

Zekai Yang, Xiaoteng Zhao, Huajin Sun, Xianting Su, Zhicheng Dong, Yilong Dong, Yukui Yu, Hongzhi Liang, Shubin Liu

Microelectron. J., 2025

A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units.

Jie Liu, Xianting Su, Zekai Yang, Zhicheng Dong, Chenxi Han, Xiaoteng Zhao, Shubin Liu

Microelectron. J., 2025

2024

A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor.

Zhicheng Dong, Shubin Liu, Xiaoteng Zhao, Baotian Hao, Xianting Su, Hongzhi Liang, Menghao Wang, Zhangming Zhu

IEEE J. Solid State Circuits, November, 2024

A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers.

Miao Zhang, Xianting Su, Zekai Yang, Zhicheng Dong, Weitan Huang, Menghao Wang, Yukui Yu, Xiaoteng Zhao, Shubin Liu, Zhangming Zhu

Proceedings of the IEEE International Conference on Integrated Circuits, 2024

A 0.0006-mm² 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS.

Zhicheng Dong, Xiaoteng Zhao, Zekai Yang, Xianting Su, Haolin Han, Feng Bu, Rong Zhou, Depeng Sun, Yong Chen, Shubin Liu, Ruixue Ding, Zhangming Zhu

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024