Zekai Yang
Orcid: 0009-0005-1710-9664
According to our database1,
Zekai Yang authored at least 11 papers
between 2024 and 2026.
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Bibliography
2026
A 0.0006-mm<sup>2</sup>, 0.13-pJ/bit, 9-21-Gb/s Sub-Sampling CDR With Inverter-Based Frequency Multiplier and Embedded 1:3 DEMUX in 65-nm CMOS.
IEEE J. Solid State Circuits, May, 2026
Distributed Model Predictive Platooning Control of Heterogenous CAVs Under Markovian Switching Communication Topologies.
IEEE Trans. Veh. Technol., January, 2026
A full-rate 8.2-to-15.1-Gb/s reference-less CDR using low-cost SAR-based frequency acquisition technique achieving 265ns acquisition time.
Microelectron. J., 2026
2025
Load-driven inductive peaking design for broad band continuous-time linear equalizer.
Microelectron. J., 2025
Withdrawal notice to "A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator" [Microelectron. J. 166 (2025) 106872].
Microelectron. J., 2025
Microelectron. J., 2025
A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units.
Microelectron. J., 2025
A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers.
Proceedings of the IEEE International Conference on Integrated Circuits, 2024
Proceedings of the Biometric Recognition - 18th Chinese Conference, 2024
A 0.0006-mm<sup>2</sup> 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024