Zhicheng Dong
Orcid: 0009-0005-3584-1453Affiliations:
- Xidian University, Xi'an, China
According to our database1,
Zhicheng Dong authored at least 18 papers
between 2023 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
A 0.0006-mm<sup>2</sup>, 0.13-pJ/bit, 9-21-Gb/s Sub-Sampling CDR With Inverter-Based Frequency Multiplier and Embedded 1:3 DEMUX in 65-nm CMOS.
IEEE J. Solid State Circuits, May, 2026
A 56-Gb/s NRZ sub-sampling CDR with improved gilbert-based frequency multiplier in 28 nm CMOS.
Microelectron. J., 2026
A 0.07-mm<sup>2</sup> 32.7-kHz Frequency Reference with Aging Calibration Embedded 1-second Timer Scoring 22% Residual Error After 500-Hour Aging at 150°C in 28-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A 1.6-to-16 GHz Sub-1-LSB INLpp 7-bit Phase Interpolator Using Constant-Load Unit with Trimming-Free Digital Calibration in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2026
2025
A Low-Noise Class-F<sub>23</sub> VCO With Harmonic Resonance Expansion and 2nd/3rd-Harmonic Outputs for Multiband mm-Wave Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2025
A 0.4-V 500-kHz FLL With Reused TDA-Based Calibration and OTA-Accelerated Technique in 65-nm CMOS for Sleep Timer.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2025
A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage.
IEEE J. Solid State Circuits, January, 2025
Load-driven inductive peaking design for broad band continuous-time linear equalizer.
Microelectron. J., 2025
Withdrawal notice to "A 56 Gb/s PAM4 slope-sampling CDR with simultaneous four-output phase interpolator" [Microelectron. J. 166 (2025) 106872].
Microelectron. J., 2025
Microelectron. J., 2025
A 7-bit 8 GHz phase interpolator with eight-phase output using a linear weighting scheme using only 50 % interpolation units.
Microelectron. J., 2025
A Reference-Less CDR Using SAR-Based Frequency-Acquisition Technique Achieving 55ns Constant Band-Searching Time and up to 63.64Gb/s/µs Acquisition Speed.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A 0.08%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator With VGS-Ratio-Based Compensation Using One-Type-Only Resistor.
IEEE J. Solid State Circuits, November, 2024
A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm<sup>2</sup> Area.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
A 0.9-V Supply Up to 21.5-dB Boost Gain Analog Front-End with T-coilloaded CTLE and VGA in 28-nm CMOS for 112-Gb/s PAM-4 Medium-Reach Receivers.
Proceedings of the IEEE International Conference on Integrated Circuits, 2024
A 0.0006-mm<sup>2</sup> 0.13-pJ/bit 9-21-Gb/s Sampling CDR with Inverter-Based Frequency Multiplier and Embedded 1: 3 DEMUX in 65-nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024
2023
A 12b 1.5GS/s Single-Channel Pipelined SAR ADC with a Pipelined Residue Amplification Stage.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A 0.012mm<sup>2</sup> 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023