Xianwu Hu
Orcid: 0000-0002-4564-127X
According to our database1,
Xianwu Hu
authored at least 8 papers
between 2012 and 2023.
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Bibliography
2023
An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2019
A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2012
J. Softw., 2012