Yufeng Xie
Orcid: 0000-0002-6541-2925Affiliations:
- Fudan University, School of Microelectronics, State Key Laboratory of Integrated Chips and Systems, Shanghai, China
- Tsinghua University, Beijing, China (PhD 2008)
According to our database1,
Yufeng Xie authored at least 23 papers
between 2010 and 2026.
Collaborative distances:
Collaborative distances:
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Bibliography
2026
A 40-nm Training-Inference STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration.
IEEE Trans. Very Large Scale Integr. Syst., January, 2026
Horizontal-Parallel ADC-less Sparsity-Clock-Aware RRAM CIM Macro for edge AI devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
A 0.562 mm<sup>2</sup> MTJ-Based Ising Machine for 48-bit Integer Factorization in 40 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2026
BLCIM: An Efficient Radix-16 Booth LUT-Based SRAM-CIM Architecture with Algorithm-Hardware Co-Optimization for NTT.
Proceedings of the Great Lakes Symposium on VLSI 2026, 2026
2025
IEEE Access, 2025
High sensing margin and parallelism 6T-2MTJ SOT-MRAM based TCAM for energy-Efficient Similarity Priority calculation in MANNs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
A 40nm STT-MRAM Near-Memory Computing Macro for Memory-Augmented Neural Network Acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
2024
Contactless Diagnosis Method and Unsupervised Learning for Panel-Level Photovoltaic Plant Operation and Maintenance.
IEEE Access, 2024
2023
An 8.8 TFLOPS/W Floating-Point RRAM-Based Compute-in-Memory Macro Using Low Latency Triangle-Style Mantissa Multiplication.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
A 40nm 150 TOPS/W High Row-Parallel MRAM Compute-in-Memory Macro with Series 3T1MTJ Bitcell for MAC Operation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
GCFP-ACIM: A 40nm 4.74TFLOPS/W General Complex Float-Point Analog Compute-in-Memory with Adaptive Power-Saving for HDR Signal Processing Applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A High Area-Efficiency RRAM-Based Strong PUF with Multi-Entropy Source and Configurable Double-Read Process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
An 8Kb 40-nm 2T2MTJ STT-MRAM Design with 2.6ns Access Time and Time-Adjustable Writing Process.
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2019
A digitalized RRAM-based Spiking Neuron Network system with 3-bit weight and unsupervised online learning scheme.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
2017
Dynamic Data-Dependent Reference to Improve Sense Margin and Speed of Magnetoresistive Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
2016
IEEE Trans. Circuits Syst. II Express Briefs, 2016
2013
A 0.13 µm 8 Mb Logic-Based Cu<sub>x</sub> Si<sub>y</sub> O ReRAM With Self-Adaptive Operation for Yield Enhancement and Power Reduction.
IEEE J. Solid State Circuits, 2013
2012
64Kb logic RRAM chip resisting physical and side-channel attacks for encryption keys storage.
IEICE Electron. Express, 2012
2011
IEICE Electron. Express, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011
2010