Aibin Yan

According to our database1, Aibin Yan authored at least 19 papers between 2014 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 




Novel Double-Node-Upset-Tolerant Memory Cell Designs Through Radiation-Hardening-by-Design and Layout.
IEEE Trans. Reliability, 2019

A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application.
IEEE Trans. on Circuits and Systems, 2019

Novel Application of Deep Learning for Adaptive Testing Based on Long Short-Term Memory.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

STAHL: A Novel Scan-Test-Aware Hardened Latch Design.
Proceedings of the 24th IEEE European Test Symposium, 2019

Single-Event Double-Upset Self-Recoverable and Single-Event Transient Pulse Filterable Latch Design for Low Power Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

T2FA: Transparent Two-Factor Authentication.
IEEE Access, 2018

Novel low cost and DNU online self-recoverable RHBD latch design for nanoscale CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS.
Proceedings of the 27th IEEE Asian Test Symposium, 2018

Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology.
IEEE Trans. VLSI Syst., 2017

Single event double-upset fully immune and transient pulse filterable latch design for nanoscale CMOS.
Microelectronics Journal, 2017

A Region-Based Through-Silicon via Repair Method for Clustered Faults.
IEICE Transactions, 2017

Highly Robust Double Node Upset Resilient Hardened Latch Design.
IEICE Transactions, 2017

A transient pulse dually filterable and online self-recoverable latch.
IEICE Electronic Express, 2017

A single event transient detector in SRAM-based FPGAs.
IEICE Electronic Express, 2017

HLDTL: High-performance, low-cost, and double node upset tolerant latch design.
Proceedings of the 35th IEEE VLSI Test Symposium, 2017

An SEU resilient, SET filterable and cost effective latch in presence of PVT variations.
Microelectronics Reliability, 2016

Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS Technology.
Proceedings of the 25th IEEE Asian Test Symposium, 2016

A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS Technology.
IEICE Transactions, 2015

Design of a Radiation Hardened Latch for Low-Power Circuits.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014